采用精确时延模型基于路径的缓冲器插入时延优化

提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束.     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的.     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的     

基于精确时延模型考虑缓冲器插入的互连线优化算法

随着VLSI电路集成度增大和特征尺寸的不断减小,连线的寄生效应不可忽略,互连线的时延在电路总时延中占了很大的比例,成为决定电路性能的主要因素.在互连时延的优化技术中,缓冲器插入是最有效的减小连线时延的方法.本文提出了一个在精确时延模型下,在布线区域内给定一些可行的缓冲器插入位置,对两端线网进行拓扑优化,并同时插入缓冲器以优化时延的多项式时间实现内的算法.我们的算法不但可以实现时延的最小化,也可以在满足时延约束的条件下,最小化缓冲器的插入数目,从而避免不必要的面积和功耗的浪费.     

CMOS缓冲器的时延估算模型

随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。为了减小互连线的影响，通常在芯片互连中插入缓冲器，但这样做会增加时延。因此，为了精确地对系统进行时延估计，必须对缓冲器的时延进行估算。基于Sakurai的器件模型，提出了一种新的缓冲器时延估算模型。     

一种适用于标准单元设计的缓冲器插入及布线算法

在考虑标准单元设计方法特点的基础上,提出了一种针对互连线时延优化的缓冲器插入及布线算法.该算法考虑标准单元设计中的缓冲器插入区域限制,在布线的同时插入缓冲器,能有效实现单路径时延最小化.     

非线性缓冲器时延模型研究

随着VLSI集成度与工作频率的提高,时延问题已成为影响芯片性能的关键因素之一。当工艺水平发展到深亚微米级,互连线时延比重已经占据总时延的绝大部分。为了减小互连线时延,缓冲器插入是当前一种常见且有效的方法。但插入缓冲器会引入新的时延问题,因而如何建立一个精确的缓冲器时延模型,是研究的重点。     

基于高阶累积量和动态统计的放电信号时延算法

为提高时延估计精度,提出了一种基于高阶累积量和动态统计的时延估计优化算法.利用高阶累积量求取放电信号的时延序列,对多组时延序列进行累加求平均,提取出时延.仿真计算结果表明:信号信噪比低于5 dB时未优化的算法判断时延会产生较大误差,而优化算法能够准确检测出信噪比低至-20 dB的放电信号的时延,且累积次数不超过100.通过对100m处实测电晕放电信号的时延求解验证了该算法的有效性和实用性.     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

时变时延的在线自适应估计

本文提出了一种时变时延的在线自适应估计新方法,首先,本文给出了一种修正的强跟踪滤波器算法,并且建立了时变时延的估计模型,基于此模型,时变时延可以被当成系统状态由修正的强跟踪滤波器算法直接进行估计,所提出的方法具有使用简单,跟踪迅速,精度高等特点,最后,仿真实验结果验证了本文方法的有效性。     

Optimal wire sizing and buffer insertion for low power and ageneralized delay model

We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize a cost function subject to given timing constraints; we focus on minimization of dynamic power dissipation, but the algorithm is also easily adaptable to, for example, area minimization. In addition, the algorithm efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. An extension of our basic algorithm accommodates a generalized delay model which takes into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. To the best of our knowledge, our approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality. The effectiveness of these methods is demonstrated experimentally     

快速片上互连缓冲器插入时序优化分析

互连线延时已成为制约大规模集成电路性能的瓶颈,而缓冲器插入能很好解决互连线延时。Van GinnekenfvGl算法是缓冲器插入互连时序优化的经典算法,针对此算法的3个主要操作过程进行改进,利用红黑树数据结构存储路由拓扑数据结构,缩短数据结构的更新访问时间;利用快速冗余判别和排序方法减小解方案数量和求解最优的复杂度。通过标准测试电路集ISCAS89中的电路对本文方法进行测试,测试结果表明,虽然随着电路规模增加,改进方法和传统方法运行时间都相应增加,但改进方法的优势更加明显;且随着缓冲器库规模的增加,其优势也越发明显,如只有一种缓冲器的缓冲器库,改进算法耗时为VG算法的73．28％,当有8种和20种缓冲器的缓冲器库时,耗时分别为VG算法的67．34％和63．05％。采用本文中的快速缓冲器插入算法,能有效缩短基于缓冲器插入的大规模互连时序优化时间。     

Interleaving buffer insertion and transistor sizing into a singleoptimization

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit, The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area delay tradeoff curves shown in this paper     

Analysis of the switching speed of BiCMOS buffer under high current

A nonlinear analytical transient response model that is suitable for BiCMOS driver circuits operating under the Kirk and Van der Ziel effect is presented. The model accounts for both base vertical push-out and lateral stretching phenomena where the forward transit time τ _f has a square law dependence on the collector current. Based on the new transient model, a closed-form BiCMOS delay expression is derived that shows excellent agreement with measured gate delay from a 0.8-μm BiCMOS technology. The comparison is made for a wide range of circuit parameters. The delay model can be used to develop timing analyzers, timing simulators, and circuit optimization tools for ULSI circuit design. As an application of the delay model, a circuit design algorithm is derived to optimize the speed-area performance of the BiCMOS buffers     

VLSI互连线的全局优化算法

介绍了通过同时插入缓冲嚣和优化线宽达到互连线时延最小化的方法。为了同时插入缓冲器、优化缓冲嚣尺寸和优化线宽，可以扩展MASM(改进激活集合法)算法。计算结果表明，该算法非常有效。     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

There have been extensive studies on timing-driven placement in recent years.Theapproaches toward this problem fall into two main categories:net-based and path-based.In a typical net-based one,potential critical paths and acceptable d...