一种适用于标准单元设计的缓冲器插入及布线算法

在考虑标准单元设计方法特点的基础上,提出了一种针对互连线时延优化的缓冲器插入及布线算法.该算法考虑标准单元设计中的缓冲器插入区域限制,在布线的同时插入缓冲器,能有效实现单路径时延最小化.     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的.     

采用精确时延模型基于路径的缓冲器插入时延优化

提出了一种基于路径的缓冲器插入时延优化算法 ,算法采用高阶模型估计连线时延 ,用基于查表的非线性时延模型估计门延迟 .在基于路径的时延分析基础上 ,提出了缓冲器插入的时延优化启发式算法 .工业测试实例实验表明 ,该算法能够有效地优化电路时延 ,满足时延约束     

采用精确时延模型基于路径的缓冲器插入时延优化

提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束.     

VLSI互连线的全局优化算法

介绍了通过同时插入缓冲嚣和优化线宽达到互连线时延最小化的方法。为了同时插入缓冲器、优化缓冲嚣尺寸和优化线宽，可以扩展MASM(改进激活集合法)算法。计算结果表明，该算法非常有效。     

SOC布图设计中的互连优化算法

使用Elmore时延模型,对二端连线的缓冲器插入方法进行了详细的讨论.给出了最小时延下,缓冲器的最佳数量和位置;同时给出了在一定时延约束条件下的缓冲器的最小数量及位置;并在典型的0 .18μm工艺参数条件下进行了测试.测试结果显示,缓冲器插入方法可以显著地减小线上的时延,而且缓冲器的数目将随着时延约束的放宽而迅速下降.当时延约束仅比最优时延多5 %时,插入的缓冲器数目就降到了最佳缓冲器数的70 %左右,这一结果对缓冲器插入算法具有普遍的指导意义.     

SOC布图设计中的互连优化算法

使用Elmore时延模型,对二端连线的缓冲器插入方法进行了详细的讨论.给出了最小时延下,缓冲器的最佳数量和位置;同时给出了在一定时延约束条件下的缓冲器的最小数量及位置;并在典型的0.18μm工艺参数条件下进行了测试.测试结果显示,缓冲器插入方法可以显著地减小线上的时延,而且缓冲器的数目将随着时延约束的放宽而迅速下降.当时延约束仅比最优时延多5%时,插入的缓冲器数目就降到了最佳缓冲器数的70%左右,这一结果对缓冲器插入算法具有普遍的指导意义.     

VLSI互联线的延时优化研究

首先对互连线模型进行了分析,介绍了插入缓冲器来减小长线延时的方法,然后通过具体计算分析了缓冲器插入的位置、数量,以及尺寸对连线延迟的影响,得出了理论上最理想的优化方案,并给出了结合实际物理设计的优化方案和算法.最后,对一条长互联线的延迟进行了仿真计算,结果证明所给出的算法可有效地减小延时.     

受摆率约束的缓冲器插入设计优化方法

随着VLSI集成度的提高,缓冲器插入技术作为一种互连优化方法,在系统设计中得到了广泛的应用。提出一种针对片上互连网络的缓冲器插入方法,求解在摆率约束下的缓冲器最优插入问题。该方法由两阶段算法组成,首先对待优化互连线网进行分段,以求解可行的缓冲器插入位置集合,其次在所求得的上述位置集合中求解摆率约束条件下的最小代价缓冲器插入问题。在0.13 μm CMOS工艺下进行电路设计,实验结果表明,相较于延时最优缓冲器插入方法,该方法所得优化结果能够满足实际电路的摆率约束,同时获得最小超过30%的面积改善比率。     

Buffer block planning for interconnect planning and prediction

This paper studies buffer block planning (BBP) for interconnect planning and prediction in deep submicron designs. We first introduce the concept of a feasible region for buffer insertion, and derive its closed-form formula. We observe that the feasible region for a buffer is quite large in general even under fairly tight delay constraint. Therefore, it gives a lot of flexibility to plan for buffer locations. We then develop an effective BBP algorithm to perform buffer clustering such that design objectives such as overall chip area and the number of buffer blocks can be minimized. Effective BBP can plan and predict system-level interconnect by construction, so that accurate interconnect information can be used in early design stages to ensure design closure     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

快速buffer添加算法

在深亚微米设计中,连线延迟时间已经超过器件延迟时间,成为影响性能的瓶颈之一。在线网中插入缓冲器（buffer）是改善线延迟的一种有效方法,但是目前基于缓冲器块（bufferblock）的方法一般因其计算量比较大,算法比较慢,并且也增加布局（floorplan）的复杂性。为此本文提出并实现了一种新的快速算法来解决芯片顶层互连中缓冲器添加问题。     

Delay analysis of buffer inserted sub-threshold interconnects

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.     

POMR: a power-aware interconnect optimization methodology

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.     

Design of tapered buffers with local interconnect capacitance

This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C³RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore, the propagation delay of each buffer stage also remains constant. Reductions in power dissipation of up to 22% and reductions in active area of up to 46%, coupled with reductions in propagation delay of up to 2%, as compared with tapered buffers which neglect local interconnect capacitance, are exhibited for an example buffer system