An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

This paper describes a 14-b direct digital frequency synthesizer (DDFS) utilizing a sigma-delta noise shaping technique to reduce spurs arising from phase truncation. A new phase accumulator architecture adopting a second-order sigma-delta modulator is proposed. The sigma-delta noise shaping eliminates periodicity inherent in the phase truncation error. With the proposed phase accumulator, the significant spurs are reduced, and the spectral characteristics of the DDFS are then determined by finite precision of sine-amplitude output. A prototype DDFS IC in 0.25-/spl mu/m CMOS was fabricated on 0.12-mm/sup 2/ die area. The measured spurious-free dynamic range (SFDR) is greater than 110 dB for 16-b phase value and 14-b sine-amplitude output. The fabricated IC consumes 100 mW with a 2.5-V supply, and correctly operates up to 250 MHz.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-/spl mu/m SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6/spl plusmn/ 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage.     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

A low-jitter mutual-correlated pulsewidth control loop circuit

This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 /spl mu/m 1P4M CMOS process. The area of the PWCL is 136 /spl times/ 143 /spl mu/m/sup 2/. At an operating frequency of 300 MHz, the power dissipation and voltage ripple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42-ps jitter at an operating frequency of 900 MHz.     

A low-power half-delay-line fast skew-compensation circuit

A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-/spl mu/m CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600/spl sim/800 MHz, as designed, with a power consumption of 25/spl sim/36 /spl mu/W/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively.     

A micropower logarithmic A/D with offset and temperature compensation

Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear range transconductor to perform voltage-to-current conversion, and a dual-slope auto- zeroing topology with 60 dB of dynamic range for sampling the envelope of speech signals. The temperature dependence of the logarithm inherent in a diode implementation is automatically cancelled in our circuit topology. Experimental results from a 1.5-/spl mu/m 3-V BiCMOS process show that the converter achieves a temperature stability lower than 150 ppm//spl deg/C from 12/spl deg/C to 42/spl deg/C, and consumes only 3 /spl mu/W of power when sampling at 300 Hz. At this level of power consumption, we show that the design is thermal-noise limited to 8 bits of precision. This level of precision is more than adequate for deaf patients and for speech recognition front-ends. The power consumption is almost two orders of magnitude lower than state-of-the-art DSP implementations, and the use of a local feedback topology achieves a 2.5-bit improvement over conventional dual-slope designs.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

Low phase noise IP VCO for multistandard communication using a 0.35-/spl mu/m BiCMOS SiGe technology

In this letter, we report that a commonly used 0.35-/spl mu/m, 60-GHz-F/sub MAX/ BiCMOS SiGe monolithic microwave integrated circuit (MMIC) technology is able to provide very low phase noise signal generation in the X-band frequency range. This statement has been demonstrated using a differential LC voltage-controlled oscillator (VCO) in which varactors are realized with metal-oxide semiconductor (MOS) transistors and inductors with a patterned ground shield technology. This VCO features an output power signal in the range of -5 dBm and exhibits a phase noise of -96 dBc/Hz at a frequency offset of 100kHz from carrier and -120 dBc/Hz at a frequency offset of 1 MHz. The VCO features a tuning range of 430 MHz or 4.3% of its operating frequency. Its power consumption is in the range of 70 mW (200 mW with buffers circuits) for a chip size of 800/spl times/1000 /spl mu/m/sup 2/ (including RF probe pads).     

Switched-current circuits in digital CMOS technology with low charge-injection errors

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.     

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.     

A Pipelined 330-MHz Multiplier

An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.