高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

Correlation between oxide breakdown and defects in SiC wafers

A correlation between gate oxide breakdown in metal oxide semiconductor (MOS) capacitor structures and structural defects in SiC wafers is reported. The oxide breakdown under high applied fields, in the accumulation regime of the MOS capacitor structure, is observed to occur at locations corresponding to the edge of bulk structural defects in the SiC wafer such as polytype inclusions, regions of crystallographic misorientation, or different doping concentration. Breakdown measurements on more than 50 different MOS structures did not indicate any failure of the oxide exactly above a micropipe. The scatter in the oxide breakdown field across a 10 mm × 10 mm square area was about 50%, and the highest breakdown field obtained was close to 8 MV/cm.     

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.     

Investigation of MOS capacitors with thin ZrO2layers and various gate materials for advanced DRAM applications

Thin ZrO2layers were used to realize MOS capacitors with aluminum, polysilicon, and molybdenum gate electrodes. The layers, 300-600 Å in thickness, were obtained by metal organic chemical vapor deposition. The effects of various high-temperature treatments as well as gate material deposition conditions on the MOS capacitor properties were studied. Processing conditions compatible with standard silicon technology were established to obtain capacitors suitable for advanced DRAM application. Relative dielectric constant ∈ ≥ 16, breakdown fieldE_{B} ge 3MV/cm, and leakage currents at applied voltage of 5V around 10^-8A/cm²enable the realization of capacitors with dielectric layer equivalent to 35 Å of SiO2.     

3.4nm超薄SiO2栅介质的特性

用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品,通过对样品进行I-V特性和恒流应力下V-t特性的测试,分析用氮气稀释氧化法制备的栅介质的性能,同时考察了硼扩散对栅介质性能的影响.实验结果表明,制备出的3.4nm SiO₂栅介质的平均击穿场强为16.7MV/cm,在恒流应力下发生软击穿,平均击穿电荷为2.7C/cm².栅介质厚度相同的情况下,P⁺栅样品的击穿场强和软击穿电荷都低于N⁺栅样品.     

Gate dielectrics for Si,SiC, and GaN as synthesized by jet vapor deposition

The principle of the Jet-Vapor Deposition (JVD) technique for thin dielectric deposition will be introduced, the properties of JVD silicon nitride (SiN), silicon oxide, and oxide/nitride/oxide (ONO) stacks as MOS gate dielectrics for Si, SiC, and GaN will be presented.     

Lateral n-channel inversion mode 4H-SiC MOSFETs

Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm²/V·s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高3nm栅氧W/TiN叠层栅MOS电容的性能.实验选取了合适的TiN厚度来减小应力,以较小的TiN溅射率避免溅射过程对栅介质的损伤,并采用了较高的N2/Ar比率在TiN溅射过程中进一步氮化了栅介质.实验得到了高质量的C-V曲线,并成功地把Nss(表面态密度)降低到了8×1010/cm2以下,达到了与多晶硅栅MOS电容相当的水平.     

An area-variable MOS varicap and its application in programmable TAP weighting of CCD transversal filters

A new three-terminal MOS varicap is proposed where the terminal capacitors are made voltage variable not by the modulation of depletion width but by changing the area of inversion under the gate. An MOS capacitor realized on silicon with an impurity gradient along the surface provides the control on the area of inversion because the gate threshold voltage is determined by the doping concentration at the surface. The inhomogeneous doping along the surface is implemented making use of the lateral diffusion from a doped oxide surface. Fabrication details of the capacitor compatible with n-channel silicon gate technology are presented. The C-V relationship for the terminal capacitors is simulated by a piecewise model and agreement with measured results is shown. The Area-Variable MOS Varicap (AVMOSV) is used in implementing an electrically programmable CCD filter with variable TAP weighting. Computer simulation shows considerable promise of area-variable capacitors in TAP weight control and transversal filter realization. Preliminary performance characteristics of a programmable CCD filter are presented.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

InGaP/InGaAs MOS-PHEMT with a nanoscale liquid phase-oxidized InGaP dielectric

InGaP/InGaAs metal–oxide–semiconductor (MOS) pseudomorphic high-electron-mobility transistor (PHEMT) with a nanoscale liquid phase-oxidized InGaP as the gate dielectric is demonstrated. Not only does the MOS-PHEMT have the advantages of the MOS structure, but it also has high-carrier density and a high-mobility 2DEG channel. Using selective oxidation of InGaP by liquid phase oxidation, the MOS-PHEMT can be fabricated without additional recess processes. The MOS-PHEMT exhibits larger transconductance, lower gate leakage current, higher breakdown voltage, higher cut-off frequency, lower minimum noise figure, and higher power-added efficiency than does its counterpart (reference PHEMT). The interface roughness effect on the DC and RF performance of devices is also discussed.     

PECVD淀积介质层对MOSFET性能的影响

通过对nMOS器件随天线比增加的阈值电压漂移、跨导变化，MOS电容在TDDB测试后的QBD退化分析来评估在RIE（Reactive Ion Etching）金属前PECVD-TEOS预淀积保护介质层的保护作用，实验结果表明此介质层没有起到足够的保护作用，反而会由于更长的等离子体工艺时间产生更严重的损伤问题。传统的电荷在硅片表面积累理论不足以解释此现象，本文从高能电子隧穿作用来分析此性能退化的原因。     

Gate oxide reliabilities in MOS (metal-oxide-semiconductor) structures with Ti-polycide gates

We have investigated the thermal degradation of gate oxide in metal-oxide-semiconductor (MOS) structures with Ti-polycide gates. We found that the Ti-diffusion into the underlying polysilicon and consequently to the gate oxide occurs upon thermal cycling processes, which results in the dielectric breakdown of the gate oxide. We also found that the Ti-diffusion is suppressed by the employment of the thin (about 5 nm) titanium nitride (TiN) diffusion barrier layer, which consequently improved the reliability characterisitics of gate oxide significantly.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device

The electrical properties of HfO₂ gate dielectric as a MOS structure deposited using Dense Plasma Focus (DPF) device under different ambient gases were investigated. DPF is unique machine used for the first time to fabricate a MOS device as it can be used to deposit dielectric film in one shot and can also be used to change the properties of the thin film surface. The films were first deposited under pre-optimized conditions of DPF device to have best focus for producing ions. The substrate for deposition of dielectric material was placed at a distance of 5 cm from the focus under argon ambient and then under nitrogen ambient. The I-V, C-V characteristics of the dielectric film were investigated employing Al-HfO₂-Si MOS capacitor structure deposited using DPF. The MOS devices were studied to determine electrical parameters like breakdown voltage, oxide charges and leakage current deposited under two different gas ambient. The microstructure of thin film is examined by using AFM and the thickness of the film is examined using an ellipsometer. The reduction in surface roughness, shift in Flat-band voltage (V_fb) and reduction in oxide-charge density (Q_ox) is seen maximum for MOS capacitor where HfO₂ as gate dielectric is deposited under nitrogen ambient using DPF machine.     

6H－SiC MOS结构电特性及其辐照效应的研究

对SiC MOS结构辐照引起的电参数退化及其电特性进行了研究。结果说明:在氧化层电场较高时Fowler-Nordheim隧穿电流决定着SiC MOS结构的漏电流,当幅照栅偏压为高的正电压时,电离幅照对SiC MOS电容的影响会更明显,SiC MOS器件比Si器件具有好的抗辐照的能力,在58kGy(Si)的辐照剂量下,其平带电压漂移不超过2V。     

Annealing of radiation-induced positive charge in MOS devices with aluminum and polysilicon gate contacts

This paper discusses the removal of radiation-induced positive charge from MOS structures by low temperature thermal anneals. Results are presented for structures in which the gate oxide is covered either by an aluminum or by a polysilicon contact during the anneal. The anneals were performed in forming gas, nitrogen and hydrogen ambients. The presence of aluminum over the gate oxide is found to play an important role in the annealing of radiation-induced positive charge in these structures . While a 400?C anneal is sufficient to remove this charge from capacit or structures with aluminum gates, it leaves a small amount of residual charge (about 6xl0¹⁰}cm²}) in structures with polysilicon gates. Anneals at temperatures in excess of 550?C are required to remove this charge completely from the polysilicon-gated MOS devices. However when a thin layer of aluminum is present over the polysilicon contact during the anneal the charge can be removed easily at 400?C. The results in capacitor structures are consistent with those found in polysilicon gate MOSFET’s with similar coverage over the gate oxide.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO₂) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n⁺-polySi) gate. The analysis utilizes the measured gate current density J_G at high oxide fields E_ox in 5.4 to 12 nm thick SiO₂ films between 25 and 300℃. The leakage current measured up to 300℃ was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n⁺-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO₂ conduction band (CB). It was observed that PF emission current I_PF dominates FN electron tunneling current I_FN at oxide electric fields E_ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO₂ films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.