SOI数模混合集成电路的串扰特性分析

采用二维TMA Medici模拟软件对SOI结构的串扰特性进行了分析.模拟发现随着频率的增加,SOI的埋氧化物对串扰噪声几乎不起隔离作用,同时,连接SOI结构的背衬底可以在很大程度上减小串扰的影响.还对减少串扰的沟槽隔离工艺、保护环及差分结构的有效性进行了比较分析,对一些外部寄生参数对串扰的影响也进行了研究.并给出了SOI结构厚膜和薄膜结构体掺杂浓度对噪声耦合的影响,所得到的结果对设计低噪声耦合的SOI数模混合集成电路具有指导性的作用.     

高速数字电路PCB中串扰问题的研究与仿真

针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。     

机载线缆间的串扰耦合分析

串扰是机载设备间互联线缆干扰耦合的重要因素。以混合模S参数为基础,建立单线-双绞线模型以模拟机载设备之间的动力线缆对信号线产生的串扰耦合。在此模型基础上提出串扰耦合测试方案,搭建串扰耦合测试系统,并根据测试获得的耦合系数评估单线-双绞线线间串扰耦合强弱。通过测试比较,对影响因素进行分析,结果表明,距地高度对线间串扰影响不大,线间距对线间串扰耦合影响显著,因此在条件允许下尽可能增加设备间互联线缆的间距可有效抑制串扰耦合。     

超深亚微米集成电路串扰估计及优化

采用RLC模型来估计互连线间的耦合噪声并对模拟结果进行分析,在此基础上,提出了几种不同的算法实现了带串扰约束的集成电路布线结果调整.     

超深亚微米集成电路串扰估计及优化

采用RLC模型来估计互连线间的耦合噪声并对模拟结果进行分析,在此基础上,提出了几种不同的算法实现了带串扰约束的集成电路布线结果调整.     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

深亚微米工艺下互连线串扰问题的研究与进展

集成电路工艺发展到深亚微米技术后,互连线串扰问题变得越来越严重,尤其在千兆赫兹的设计中,耦合电感的影响不能忽略.插入屏蔽的操作成为减小耦合电感噪声的有效方法.文中首先介绍共面、微带状线和带状线三种互连结构下的电感耦合特性,然后分别介绍了基于共面互连结构的用于计算互连线噪声的Keff模型和RLC精确噪声模型.实验表明两种模型都有很高的精确度,在解决互连线串扰的物理设计中有广泛的应用.     

深亚微米工艺下互连线串扰问题的研究与进展

集成电路工艺发展到深亚微米技术后,互连线串扰问题变得越来越严重,尤其在千兆赫兹的设计中,耦合电感的影响不能忽略.插入屏蔽的操作成为减小耦合电感噪声的有效方法.文中首先介绍共面、微带状线和带状线三种互连结构下的电感耦合特性,然后分别介绍了基于共面互连结构的用于计算互连线噪声的Keff模型和RL C精确噪声模型.实验表明两种模型都有很高的精确度,在解决互连线串扰的物理设计中有广泛的应用     

降低有损耦合微带线间串扰的方法分析

为降低和控制有损耦合微带线间的串扰,在强信号线两边各插入了一列用金属填充的、顶端用微带连接的接地孔.利用FDTD方法对该结构进行模拟并利用FEM法进行了验证.模拟结果表明串扰衰减程度与基底介质的损耗、接地孔参数有关.     

串扰噪声及串扰噪声模型的分析

随着集成电路设计到达深亚微米领域,互连线间的串扰噪声影响越来越大,日益成为与功耗、速度、面积等一样重要的影响因素,目前已发展出多个精确度和时间复杂度不同的串扰噪声模型.本文在对串扰噪声和现有串扰噪声模型深入理解的基础上,提出了三个新的串扰噪声模型,并将它们与现有的串扰噪声模型进行分析比较,指出它们各自的优缺点及适用范围,从而为选择高精确度、良好一致性、时间复杂度低的模型提供参考.     

A dual body SOI structure for mixed analog-digital mode circuits

A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFET's are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body resistance, and the self-heating effect, it is shown that the proposed structure is promising for SOI technology in mixed analog-digital mode circuit applications     

Comparative study of fully depleted and body-grounded non fullydepleted SOI MOSFETs for high performance analog and mixed signalcircuits

This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFET's with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFET's are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits     

A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.     

Analysis and experimental verification of digital substrate noisegeneration for epi-type substrates

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends     

Measuring and modeling the effects of substrate noise on the LNAfor a CMOS GPS receiver

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output     

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.     

Measurements and analysis of PLL jitter caused by digital switchingnoise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-μm digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

地平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。本文就如何正确的分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

参考平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。文章就如何正确地分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。