High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a modulator. This design algorithm includes the advantages from both single-bit M and multi-bit M. This paper utilizes a second order lowpass modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current -modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 m CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other -modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current -modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor -modulators.     

Redundancy Removal during High-Level Synthesis Using Scheduling Don‘t-Cares

Previous work in automata theory has shown how to eliminate sequential redundancy from networks of FSMs by finding sequences of inputs and outputs which are never communicated between components of the network. This paper shows that behavior automata—finite-state machines whose inputs and outputs are incompletely scheduled—exhibit similar properties. Using the behavior FSM (BFSM) as a model for scheduling, we show how to identify and eliminate both input and output scheduling dont-cares. When a scheduling dont-care is eliminated from a network of BFSMs, the register-transfer implementation is guaranteed not to suffer from the corresponding dont-care sequence. A definition of scheduling dont-cares improves our understanding of the foundations of high-level synthesis and the relationship between high-level and sequential optimization. In practice, scheduling dont-care elimination is a powerful tool for eliminating redundancy early in the design process.     

An algorithm for stability determination of two-dimensional delta-operator formulated discrete-time systems

The recent interest in delta-operator (or, -operator) formulated discrete-time systems (or, -systems) is due mainly to (a) their superior finite wordlength characteristics as compared to their more conventional shift-operator (or,q-operator) counterparts (or,q-systems), and (b) the possibility of a more unified treatment of both continuous- and discrete-time systems. With such advantages, design, analysis, and implementation of two-dimensional (2-D) discrete-time systems using the -operator is indeed warranted. Towards this end, the work in this paper addresses the development of an easily implementabledirect algorithm for stability checking of 2-D -system transfer function models.Indirect methods that utilize transformation techniques are not pursued since they can be numerically unreliable. In developing such an algorithm, a tabular form for stability checking of -system characteristic polynomials with complex-valued coefficients and certain quantities that may be regarded as their corresponding Schur-Cohn minors are also proposed.     

Asymptotic behavior of periodicH ∞ a posteriori filters

The asymptotic behavior of linear periodic discrete-timeH a posteriori filters is discussed in this paper. We extend existing results for time-invariantH filters to study the problems arising from periodic discrete-time systems. Based on quasi-lifting techniques, a sufficient condition for ensuring feasibility and convergence ofH a posteriori filters is given.     

A Modular Phase-Frequency Detector Design with ±2nπ Linear Range of Operation

To extend the linearity range of the phase-frequency detector/charge pump (PFD/CP) circuit, a modular design for a novel PFD architecture is proposed. The new circuit yields a modular extension range of –2N to 2N, where N is an integer representing the order of the PFD/CP extension. The efficacy of the new PFD/CP is demonstrated by the improved frequency acquisition time obtained via closed-loop simulation. Hence, the developed architecture is a good candidate for phase-locked loops requiring the use of PFD/CP with a broad linear range of operation.     

An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.     

A Small Area Charge Sensitive Readout Chain with a Dual Mode of Operation

A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is . The gain at the shaper output is 378 mv/fC, theENC is 16 rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF.     

Solutions for H∞ Filtering of Two-Dimensional Systems

Thispaper deals with the H filtering problemfor linear discrete-time two-dimensional (2-D) systems describedby the Roesser model. It firstly establishes a version of thebounded real lemma to give a sufficient condition for quantificationof the H noise attenuation for 2-D systems.Based on the bounded real lemma, the H filteringproblem is investigated for filters of an observer-based structureor a general state equation form and the solutions are obtainedin terms of Riccati inequalities or linear matrix inequalities.The design approach is illustrated by an example of a stationaryfield in image processing.     

A Novel Calibration Method for Phase-Locked Loops

A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter to measure the natural frequency of the PLL; moreover it is capable of estimating the static phase offset. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.This work was carried out as a part of an internship at the QCT department of Qualcomm CDMA Technologies.Marco Cassia was born in Bergamo, Italy, 1974. He received the M.Sc. degree in engineering from the Technical University of Denmark, Lyngby, Denmark, in May 2000 and the M.Sc. degree in electrical engineering from Politecnico di Milano, Italy, in July 2000.From July 2001 to July 2002 he was with the QCT department of Qualcomm CDMA Technologies, San Diego, working in the field of direct modulation synthesizers. He is currently working toward the Ph.D.degree at the Technical University of Denmark.His main research interests are in the areas of low-power low-voltage RF systems.Peter Shah was born in Copenhagen Denmark in 1966. He completed his MScEE and Ph.D at The Technical University of Denmark in 1990 and 1993 respectively. From 1993 to 1995 he was a post doctoral research assistant at Imperial College in London, England, working on switched-current circuits. In 1996 he joined PCSI in San Diego (subsequently acquired by Conexant) as an RFIC design engineer, working on transceiver chips for the PHS cellular phone system. In 1998 he joined Qualcomm, also in San Diego, where he worked on RFICs for CDMA mobile phones and for GPS. In December 2002 he joined RFMagic where he is currently working on RFICs for consumer electronics. His research interests lie mainly in RFIC architecture and design, including sigma-delta PLLs and A/D and D/A converters, LNAs, mixers, and continuous-time filters.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I²L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ØrstedDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

New results in 2D optimal control theory

The infinite horizon optimal control problem is solved for 2D systems described by the Fornasini-Marchesini model. An ₂-approach permits us to reduce the optimal control problem to a norm minimization one in Hilbert spaces. Both necessary and sufficient conditions for solvability and the structure of the solution are established. Moreover, a comparison with known results is presented, and the singularities of the 2D Riccati equation are examined in order to characterize suboptimal control laws that apply whenever the solvability conditions are not satisfied.     

An H<Superscript>∞</Superscript> Output Feedback Control for Discrete-Time State-Delayed Systems

A coprime factorization approach to H controller design for discrete-time state-delayed systems is developed. The coprime factors that are generated by the present factorization possess the same delayed state as that of the original system. This property, together with the well-known Youla parameterization and the chain-scattering matrix setting, provides a relatively simple method for obtaining a family of internally stabilizing H output feedback controllers. A numerical example is given to demonstrate the validity and applicability of the proposed approach.     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

H ∞ and Robust Control of 2-D Systems in FM Second Model

This paper deals with output feedback stabilization and H control problems for two-dimensional (2-D) discrete linear systems without or with parameter uncertainty. The class of systems under investigation is described by the 2-D local state space Fornasini-Marchesini second model. We aim at designing a dynamical output feedback controller to achieve asymptotic stability and H performance for the 2-D system. It is shown that the design of output feedback controller can be recast into a convex optimization problem characterized by linear matrix inequalities (LMIs). The LMI solution is further extended to solve the robust stabilization problem for 2-D systems subject to norm-bounded uncertainty. The solutions for the H control and robust stabilization are applied to two application examples: thermal process control and robust stabilization of processes in Darboux equation.     

Envelope-constrained IIR filter design: An LMIH ∞ optimization approach

In this paper, we consider envelope-constrained (EC) infinite impulse response (IIR) filtering problems. The aim is to design an IIR filter such that theH norm of the filtering error transfer function is minimized subject to the constraint that the estimation error with a given input to the linear dynamic system is contained or bounded in a prescribed envelope. The filter design problem is formulated as a standard optimization problem in linear matrix inequalities (LMIs).     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

Editorial

Future integrated microsystems will benefit significantlyfrom progress in the VLSI field. Two key elements will boostthe implementation of new micro-integrated architectures: progressin batch-manufactured silicon sensors and the introduction ofnew circuit techniques for designing interface circuits. Thesetwo factors will be essential in favoring the transition fromthe present research driven speculations to customer drivenactivities. This paper discusses the key issues in realizingmicrosensors and the most suitable circuit techniques for interfacingand processing their output signals. A number of examples ofintegrated structures will illustrate present problems and possiblesolutions.     

Theory of PLL fractional-N frequency synthesizers

This paper presents an overview of the evolution of frequency synthesizers based on phase-locked loops (PLLs). The main limitations of the digital PLLs are described, and the consequent necessity of using fractional-N techniques is justified. The origin of the typical spurious noise lines on the sidelobes of the synthesized frequency is explained. It is shown how to eliminate these spurious noise lines by using digital modulators to control the frequency division value. Finally, the implications of using digital modulators together with fractional-N PLLs on the output phase noise are analysed.     

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 m TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.