视频胶囊内窥镜的改进设计与实验

为延长视频胶囊内窥镜工作时间,提高体外接收视频质量,需降低胶囊内射频电路模块的功耗以改进发射电路的发射效果.针对上述问题,本文设计了胶囊内的射频电路模块和螺旋形发射天线,并使用ADS2011及HFSS对其进行仿真,最后通过实验对该设计进行验证.内窥镜胶囊进入活体动物(猪)胃肠道后,体外便携接收器接收到的视频图像质量较高,证明该改进设计可行.结果表明:当射频电路板的直径为9.8mm,射频模块的工作频率为1.0GHz,功耗为15.9 mW时,胶囊的工作时间为9.0h,视频数据的无线传输速率达到30 frame/s(320×240 pixel/frame).     

小功率无线数字收发系统的设计

无线数据传输已广泛地运用在工业数据采集系统、安全防火系统、无线遥控系统、生物信号采集、机器人控制、数据通信、数字音频、数字图像传输等领域中。人类已经步入了信息时代,无线控制将会占有越来越重要的地位,它的广泛应用将会给我们的生活和工作带来方便。本文主要研究了无线收发系统与信号采集电路相结合,以完成对无人区域的信息采集,它将会对这些区域的研究作出重要的贡献。它主要由发射电路和接收电路组成。发射电路由传感器,模/数转换电路,编码电路,发射模块组成;接收电路由接收模块,解码电路,显示电路组成。     

智能光模块中可变阈值的信号丢失检测电路

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了一种新型可用于智能光模块的可变阈值信号丢失(LOS)检测电路,电路利用光接收机中的限幅放大器组成准对数律接收信号强度指示电路.该指示电路与迟滞比较器、基准参考源、运算放大器和两个外部调节电阻组成了可变报警阈值的LOS检测电路.整个电路工作于5V单电源供电,功耗为60mW.测试结果表明,对于155Mbps的输入信号,信号检测的动态范围高达60dB,对数精度小于2dB.可变报警阈值范围为1～700mV,同时保证报警迟滞宽度为4dB左右.良好的性能预示了该电路潜在的商业前景.     

智能光模块中可变阈值的信号丢失检测电路

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了一种新型可用于智能光模块的可变阈值信号丢失(LOS)检测电路,电路利用光接收机中的限幅放大器组成准对数律接收信号强度指示电路.该指示电路与迟滞比较器、基准参考源、运算放大器和两个外部调节电阻组成了可变报警阈值的LOS检测电路.整个电路工作于5V单电源供电,功耗为60mW.测试结果表明,对于155Mbps的输入信号,信号检测的动态范围高达60dB,对数精度小于2dB.可变报警阈值范围为1～700mV,同时保证报警迟滞宽度为4dB左右.良好的性能预示了该电路潜在的商业前景.     

频率测量单片集成电路的研究

介绍了等精度测频的基本原理,以此为基础,设计了一种用于测量射频信号频率的单片集成电路.着重阐述了频率测量单片集成电路的构成和高频信号转换电路的设计.该电路芯片在0.18μm CMOS标准工艺线上完成了制作,封装于CQFP48中.经测试,测频范围可达40～1500 MHz,测频误差小于0.8 MHz,功耗小于100 mW.     

电压激励神经信号重建微电子系统

采用0.6 μm CMOS工艺设计并仿真了电压激励的神经信号重建微电子系统.系统适用于卡肤电极(cuff electrode),由检测电路和功能电激励(FES)路组成.检测电路采集受损神经上端信号,以控制功能电激励电路,产生FES信号来激励受损神经下端.电路工作于±2.5 V.系统增益40～80 dB可调,3 dB带宽大于10 kHz,功耗8.2 mW.芯片尺寸为1.42 mm×1.34 mm.     

基于差分编码技术的12.5 Gbit/s高速SerDes发射机

研究并设计了一种基于差分编码技术的12.5 Gbit/s高速SerDes发射机。该电路由并串转换模块、去加重控制模块和驱动模块组成。驱动模块采用电流模逻辑异或门结构,动态负载的加入可以在降低功耗的同时实现与传输线的阻抗匹配。首次提出在并串转换模块中加入差分编码电路的解决方案,以保证原码输出,从而使数据在发射机内完成差分编解码的过程。后仿真结果表明,发射机数据传输速度达到12.5 Gbit/s。此时发射机整体功耗为39 mW,输出总抖动为0.05 UI,远小于JESD204B标准所要求的0.3 UI。     

光接收机用0.5mV高灵敏度带有接收信号强度指示的200MbpsCMOS限幅放大器

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了0.5mV高灵敏度,72dB超宽动态范围的200Mbps CMOS限幅放大器.该电路详细分析和设计了一种新型的有源直流漂移消除环路获得这一性能.利用信号通路中的限幅放大器,实现了基于分段线性近似的接收信号强度指示电路.信号检测的动态范围高达60dB,对数精度小于2dB.整个电路在5V单电源下工作,功耗为60mW.芯片有效面积为1.05mm2.     

模拟用户接口电路

本文介绍用于1240数字程控交换机模拟用户模块的专用大规模集成电路(简称MBLIC)。它采用高压(70V)BIMOS工艺,芯片尺寸5.5×5.6(mm),28脚双列直插陶瓷封装,功耗400mW(典型值)。MBLIC主要完成以下功能: 1.向用户线馈电; 2.AC/DC回路阻抗合成; 3.将语音信号和12/16kHz计费信号耦合到用户线; 4.实现二/四线转换; 5.用     

一种0.13μm混合信号CMOS高速USB 2.0收发器

研制了一种采用0.13μm混合信号CMOS工艺的高速USB 2.0收发器.为适应工艺和系统指标的要求,改进了高速电流模式差分比较器,带跳变窗口使能逻辑鉴相器和模拟连续调整共模反馈电路等电路模块的设计.电路在SMIC流片后经测试,结果表明预期功能均得以实现,发送数据抖动(方均根)小于53ps,接收误码率小于10-12,电源电压为1.2V,功耗为42.5mW,芯片面积为900μm×700μm.     

Compact 10-Gbit/s optical transmitter and receiver circuit packs

Compact wideband 10-Gbit/s optical transmitter and receiver circuit packs are realized using high speed analog and digital GaAs IC's as well as a highly thermally conductive board and appropriately designed small function block modules that employ multichip packaging and resonant cavity mode damping. To achieve a compact receiver, the receiver circuit employs a clamp and peak-detector IC in the high speed analog equalizer amplifier to obtain a constant output direct current level for any mark density imbalance in the number of ones and zeros in the signal and a variable phase-shifter IC in the timing circuit. Realized circuit pack size is 200×280×15.24 mm and the power consumption of each pack is about 25 W     

Simultaneous broadcasting of analog FM and digital audio signals bymeans of adaptive precanceling techniques

A method for broadcasting digital audio simultaneously with existing analog frequency modulation (FM) radio is presented. The method is based on precomputing the response of the host analog FM signal at the digital receiver and precanceling it at the transmitter. As a result, the digital transmission is free from interference from analog FM. We select the rate and power level of the digital transmission in a manner that the interference the digital data incur on the analog FM signal remains at acceptably low levels. The digital transmission is based on adaptive orthogonal frequency-division multiplexing (OFDM) (adaptive multicarrier). The frequencies and number of carriers of the digital multicarrier modem are judiciously selected in a time-varying fashion so as to cause a negligible distortion in a standard receiver for analog FM. Simulations based on conservative nonoptimized signal design indicate that data rates up to about 130 kb/s inside the 200-kHz FM channel are achievable for acoustic test signals. We present a number of numerical examples where the average digital data use up to 50% of the 200-kHz power spectrum with digital signal power levels 25-35 dB below the analog signal. Due to the resulting variable-rate digital transmission, a control channel is required. A method of precanceling with multiple orthogonal direct-sequence spread-spectrum schemes is also presented     

Simulation System for Analog and Digital Transmissions

In this paper a complete communication system simulation package is described, which includes digital as well as analog operations to be performed on the signal to be transmitted. The package simulates the transmitter, the communication channel, and the receiver. The digital transmission simulation considers data communication systems with digital filtering, source and channel coding performing the operations of transmitter coding and receiver decoding. The two coding operations can be realized both separately and independently and in a strictly connected or "integrated" form. The analog transmission simulation includes the modulator, the transmitter pulse shaping filter, the communication channel, the receiving filter, and the demodulator. This section is very general, so that it allows the simulation of both analog and digital transmissions. Simulation results are presented regarding some combinations of the following techniques: predictive source coding, block codes able to correct random and burst errors, and modulation techniques such as AM,M-level PSK, FSK, and MSK. In particular, the paper presents the results of the analyses of an integrated source-channel coding applied to digital transmissions and of a system transmitting both voice and data for a VHF communication link between ground and aircraft for air traffic control applications.     

一种基于FPGA的自动功率控制电路设计与实现

由于导航数字接收机模拟前端的差异性及其采用的A/D转换电路不同,导致数字中频信号功率变化范围较大,且量化后的数字信号有效比特位数有较大差异。为了优化后续的基带数字信号处理过程,提出了一种基于FPGA的自动功率控制电路的实现方案。该电路通过可变点数的求平均运算,统计出信号的直流分量,然后将去直流后的信号进行功率估计,最后由功率反馈调整单元进行增益调整,从而保证输出信号的功率基本稳定。     

Precoded Modulo-Precanceling Systems for Simulcasting Analog FM and Digital Data

We present techniques for simulcasting low-power digital data and analog FM over fading channels. Our methods have strong connections to what are referred to as dirty paper coding techniques in that a low-power digital data signal is modulo-added to the host analog FM signal. Due to the low power levels of the digital data and the suppression capability of analog FM, a standard analog FM receiver can be used to reliably recover the analog audio signal. We develop digital receivers that work reliably over fading channels given imperfect channel state information. Spreadresponse precoding is exploited to not only provide rate-1 temporal diversity benefits, but also to simplify the design of the modulo-precanceler and the receiver. Our theoretical and simulation-based performance analysis of the digital receivers and our MSE-based analog FM distortion analysis suggest that precoded modulo-precanceling schemes provide substantially higher data rates than existing precanceling strategies at the cost of transmission delay and transmitter and receiver complexity. The systems we present are also readily compatible with conventional channel coding techniques as well as with analog FM postcancelers, which can improve the digital receiver bit-error-rate performance at the expense of receiver complexity.     

A quad-band 8PSK/GMSK polar transceiver

The addition of 8PSK modulation to the GSM standard creates the need for architectural modifications to achieve necessary performance while maintaining a cost-effective solution. A large-signal polar modulation transmitter allows the use of an efficient nonlinear power amplifier (PA) for both GMSK and 8PSK. Digital interfaces are used for both receiver and transmitter, with analog options available for compatibility with older technology baseband systems. The receiver section of the transceiver is programmable to operate in direct conversion mode or multiple VLIF modes. All analog and digital filtering necessary to define the final channel is included. The transmit section of the transceiver uses an all digital system with a fractional-N digital modulator for the phase path. The amplitude path uses a Powerstar PA with both the ramp and the amplitude modulation applied to the collector. The transceiver meets or exceeds all specifications for both GMSK and 8PSK in all four cellular bands (850/900/1800/1900).     

一种抗干扰能力极强的计算机通信接口电路

设计了一种结构简单，抗干扰能力极强的计算机通信接口电路。该电路利用模拟开关实现了全数字二态电平（1，0）与三态电平(1，0，-1)之间的相互转换；利用模拟开关导通电阻的动态效应以及MOS晶体管开启电压Vτ的衬偏效应，提高了接收电路的抗干扰能力，提出了一种与共模干扰无关的模拟数字混合接收电路。     

基于MAX30102的穿戴式血氧饱和度检测系统

本文设计了一种以MAX30102血氧饱和度和心率的集成芯片为传感器,nRF52832为微处理器的穿戴式血氧饱和度检测系统。系统设计过程中充分利用MAX30102光电反射式血氧传感器集光电发射接收、数模转换、数据滤波为一体,nRF52832 Cortex-M4F微处理器集成硬FPU单元和多种无线通信协议的优点,提高了检测模块的抗干扰能力和系统的运行速度及信号处理能力,降低了系统的开发时间和系统功耗,为系统的智能化提供多平台支持。在系统的信号处理算法上,设计了多种滤波算法进行比较,并选择了性能较优适合本系统的Dtrend去趋势算法虑除基线漂移和运动伪差干扰,以实现了更为精准的穿戴式血氧饱和度检测系统的设计。     

基于spce061实现离散混沌信息加密传输的实验研究

利用spce061高速单片机和logistic映射,对声音信号进行信息加密传输实验。发送端对模拟语音信号作A/D转换,进行多级离散混沌调制,采用并行和异步串行两种方法进行传输实验。接收端采用DeadBeat同步法快速解调,然后经D/A转换输出语音,对解调产生的噪声进行分析。实验表明,多级离散混沌系统串联加密方法简单可行。     

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of$-$110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.