SYJ结型场效应管在音频电路中的应用

SYJ 型场效应管是 N 型沟道结型场效应晶体管,其结构如图1所示。在 N 型硅材料的两端引出的电极分别称为漏极(D)和源极(S),在 N 型硅材料的两侧各做一个 P型区,相连引出的电极称为栅极(G)。通过控制栅源之间电压 V_(GS)就可改变漏电流 I_D     

具有夹层的垂直U型栅极TFET的设计

通过使用工艺计算机辅助设计(TCAD)仿真技术提出了一种新型的带有夹层的垂直U型栅极隧穿场效应晶体管(TFET)结构.该器件是通过优化基于Ge的栅极金属核垂直纳米线TFET结构获得的.通过在沟道中增加重掺杂夹层,器件的平均亚阈值摆幅(SSavg)得到了改善;又通过改变器件的源极和漏极材料,器件的开关电流比(Ion/Ioff)得到了改善.对夹层的掺杂浓度和厚度以及沟道的高度也进行了优化.最终优化后的器件开态电流为220 μA/μm,关态电流为3.08×10-10μA/pm,SSavg为8.6 mV/dec,表现出了优越的性能.与初始器件相比,该器件的SSavg减小了 77％,Ion/Ioff增加了两个数量级以上.此外,提出了针对该器件的可行的制备工艺步骤.因此,认为该器件是在超低功耗应用中非常具有潜力的候选器件.     

一种TFT源漏极沟道尺寸的自动测量方法

为了实现对图像中TFT源漏极的快速定位和沟道尺寸的自动测量,采用基于图像特征点的图像识别方法。在识别过程中先采用图像处理的方法对图像进行优化,再采用多边形拟合的方法确定目标的边缘,并通过改进的角点检测方法对物体形状进行更精确的定位,从而实现了对TFT源漏极沟道尺寸的精确测量。经过实验验证,精度可达到0.02像素。     

薄膜晶体管及其在有源矩阵液晶显示中的应用

薄膜晶体管(TFT)是众多场效应晶体管(FET)中的一种。PC机及监视器等高清晰度液晶显示(LCD)中的TFT以有源矩阵的形式应用在点阵驱动的有源矩阵液晶显示器(AMLCD)中。作为开关器件，AMLCD中的TFT工作在饱和模式，其源极总是连接数据总线(视频)，漏极接像素电极。其结构为交错／反交错和共面／反共面两种基本类型。TFT的主要工艺与IC技术兼容，半导体层所用的材料主要是a—Si。     

基于以顶层ITO为像素电极设计的产品工艺优化

HADS产品通常使用有机膜材料来减小寄生电容,以实现高像素密度(PPI)显示。本文对如何改善以顶层ITO为像素电极(Pixel Top)设计的有机膜产品的公共电极ITO与数据线间短路(DCS)不良进行了工艺优化研究。首先,通过显微镜、聚焦离子束对HADS有机膜产品DCS不良发生机理进行了分析,进而提出了第一钝化绝缘层刻蚀工序省略、保留第一钝化绝缘层至公共电极与像素电极间第二钝化绝缘层刻蚀时进行"一步刻蚀"的工艺流程变更改善方案。针对新工艺流程验证中TFT栅极过孔处第一钝化绝缘层出现的底切不良,通过调整等离子增强化学气相沉积成膜参数改善第一钝化绝缘层膜质,并选取最优成膜条件进一步调整干法刻蚀参数改善刻蚀形貌,获得了优良的栅极过孔刻蚀坡度角。优化后的"一步刻蚀"工艺进行的TFT基板,其栅极过孔第一钝化绝缘层坡度角小于40°,与栅极绝缘层间无明显刻蚀台阶。量产验证有机膜缺失导致的DCS发生率降为0。通过优化工艺,在降低产品不良率的同时还减少了工艺步骤,提升了产能。     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

阵列基板栅极制程的Cu腐蚀研究

在大尺寸液晶显示器的薄膜晶体管(Thin Film Transistor,简称TFT)TFT工艺技术中,Cu正逐步取代Al作为电极材料。与Al电极制程相比,在进行栅极(Gate)制程时Cu容易发生腐蚀,这会降低产品良率。本文结合ADS(Advanced Super Demension Switch)显示模式下0+4掩膜板(mask)技术的Gate刻蚀制程和1+4掩膜版技术Gate光刻胶(Photo Resist,简称PR)剥离制程的Cu腐蚀现象进行分析,结合实验验证,确定Cu腐蚀原因,最终提出改善方案。实验结果表明:0+4mask技术的Gate制程中,ITO刻蚀液所含的HNO3会使MoNb/Cu结构电极的Cu发生电化学腐蚀;将电极结构更改为单Cu层则可以避免电化学腐蚀。在1+4mask技术的PR剥离(Strip)制程中,基板经历的剥离时间长或进行多次剥离或在剥离设备中停留,均会引起Cu腐蚀;增加剥离区间与水区间空气帘(Air Curtain)吹气量、增加TFT基板在过渡区间(H2O与剥离液接触的区间)的传输速度,管控剥离液使用时间等措施可以缓解Cu腐蚀。     

TFT-LCD器件Al电极TFT特性研究

本文对Mo/Al/Mo作为TFT-LCD器件源/漏极的TFT特性进行了研究。与单层Mo相比,存在沟道界面粗糙,I_(off)偏大问题,通过优化膜层结构,改善界面状态,得到了平整的沟道界面和良好的TFT特性。增加Bottom Mo的厚度,可以有效减少Al的渗透,防止Al-Si化合物的形成,得到界面平整的沟道;N~+刻蚀后SF6处理对特性影响不大,增加刻蚀时间可以使I_(on)和I_(off)同时降低;PVX沉积前处理气体N_2+NH_3与H_2区别不大,都可以减少沟道缺陷,而增加H_2处理时间会增强等离子的轰击作用,减少了沟道表面Al-Si化合物,但处理时间过长可能会使沟道缺陷增加;采用bottom Mo加厚,N~+刻蚀以及PVX沉积前处理等最优条件,可以得到沟道界面良好,TFT特性与单层Mo相当的TFT器件。     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管(poly-Si TFT).该poly-Si TFT由一超薄的沟道区和厚的源漏区组成.超薄沟道区可有效降低沟道内陷阱密度,而厚源漏区能保证良好的源漏接触和低的寄生电阻.沟道区和源漏区通过一低掺杂的交叠区相连接.该交叠区使得在较高偏置时,靠近漏端的沟道区电力线能充分发散,导致电场峰值显著降低.模拟结果显示该TFT漏电场峰值仅是常规TFT的一半.实验结果表明该TFT能获得好的电流饱和特性和高的击穿电压.而且,与常规器件相比,该TFT的通态电流增加了两倍,而最小关态电流减少了3.5倍     

TFT-LCD HADS显示模式下黑白Mura机理研究及设计优化

随着高分辨率TFT-LCD HADS产品的开发,一种与像素ITO图形密切相关、有明暗(黑白)亮度差异、不同视角观察下存在黑白反转现象的Mura不良高发。经过对不良产品的参数测量和模拟分析,确定发生该不良的原因是在邻近区域内,像素开口区内的像素电极ITO(1ITO)图形和公共电极ITO(2ITO)图形发生了不同程度的相对偏移,电场分布存在差异,因此亮度发生明显差异;而且由于图形间的相对偏移导致电极间的电场发生偏移,形成像素左右两侧的一侧为强电场,一侧为弱电场,因而会出现从一侧观察发亮而从另一侧观察发暗、左右视角观察的黑白反转现象。Mura区与相邻OK区1ITO?2ITO对位差异为0.5μm。通过1ITO和2ITO的线宽设计优化,可提高产品对此偏移不均一的容忍度。最终采用最佳1ITO、2ITO线宽条件生产,配合1ITO和2ITO共用设备及TP非线性补正等条件并举,此不良由高发时的14.2%降至0.2%以下。本文研究成果对于高分辨率HADS产品的设计和性能改善,有着重要的指导和参考意义。     

不同双栅极设计对a-Si:H TFT特性影响

本实验于原有的单底栅a-Si TFT产品结构下,通过增加不同的顶栅极设计方式(不同a-Si覆盖比例、不同沟道几何形貌、不同沟道W/L比例)来研究双栅极设计对a-Si TFT特性的影响。实验结果显示双栅极a-Si TFT比现行单底栅a-Si TFT可以提升I_on 7%、降低SS 3%、同时对I_off以及TFT稳定性影响不明显,显示双栅极a-Si TFT设计结构具有在不提高成本以及不变更工艺流程下,达到整体提升TFT特性的效果。顶栅极 TFT 特性不如底栅极,推测为a-Si/PVX界面不佳使得电子导通困难导致,未来可以借由改善a-Si/PVX界面工艺提升顶栅极TFT特性。     

基于柔性PI基底的氧化物IGZO TFT器件工艺及特性研究

讨论了基于柔性PI基底上的底栅型TFT器件工艺,通过工艺优化解决了双层结构干刻速率不同造成的下切角形状。本文TFT器件是基于氧化物IGZO为有源层,栅绝缘层采用Si3N4/SiO2双层结构,采用两次补偿曝光、干刻方式消除干刻引入的下切角形状,有效解决了薄膜沉积引入的断线风险。实验结果表明,经过SEM断面观察,干刻后双层结构taper角度适合TFT器件后续沉膜条件,柔性基底上制作的TFT器件迁移率达到14.8cm2/(V·s),阈值电压Vth约0.5V,亚域值摆幅SS约0.5V/decade,TFT器件的开关比Ion/Ioff106。通过此方法制作出的器件性能良好,满足LCD、OLED或电子纸的驱动要求。     

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

A new process of fabricating inverted-staggered tri-layer thin-filmtransistors

A new method of fabricating a-Si:H TFT with etching-stop structure has been proposed. Only one plasma-enhanced chemical vapor deposition is required in this new method and a PH₃/H₂ plasma treatment during the deposition has been used to form the TFT contact and thus saved another plasma deposition. With this method, a TFT of 500 Å active layer has been fabricated successfully. The drain current and saturation mobility of this device is 2.4×10^-7 A and 0.1 cm²/V sec, respectively, which is comparable to the conventional fabricating method. The plasma treatment will also form an additional leakage path on the TFT top surface and increase the TFT subthreshold slope. However, a current of less than 1 pA at V_G=-2.4 V can still be obtained. The possible mechanism of the contact formation by the plasma treatment is also discussed     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

A novel high-performance poly-silicon thin film transistor with aself-aligned thicker sub-gate oxide near the drain/source regions

Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9×10⁶ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V_GS=-15 V and V_DS=10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Carrier accumulation and space-charge-limited current flow in field-effect transistors

This paper reports an investigation of devices fabricated by lateral diffusion techniques which have non-uniform doping profiles along the channel. The application of a two-dimensional numerical method to a device model representing these devices shows carrier accumulation in the conductive channel. The increase of carrier concentration with the increasing drain-to-source voltages is caused by the interaction of the source and the drain N⁺-regions. This indicates the possibility of the space-charge-limited current which is a different conduction mechanism from that of the conventional devices. From the study of one-dimensional N⁺-N-N⁺ structures, the length-to-L_DE (extrinsic Debye length) ratio of the channel and the crossover voltage have been recognized as important parameters in realizing the space-charge-limited current. The drain characteristics of a device model with a small crossover voltage and a small length-to-L_DE ratio are obtained by a simple analysis. Triode-like characteristics are found for this model as expected.