一种低功耗环形振荡器的噪声分析与设计

介绍了一种采用CSMC 0.153 μm CMOS工艺制作的差分环形振荡器。分析了环形振荡器延时单元的选取和设计原理,以及输入差分对管跨导和负载电阻对环振相位噪声的贡献,得到负载为线性区偏置MOS管时低功耗低相位噪声环振的设计方法。在相位噪声变化较小时,采用电容阵列结构拓宽了环形振荡器频率的调谐范围。测试结果表明,该环形振荡器输出频率范围为513 MHz ~1.8 GHz;在振荡频率为1.57 GHz频偏1 MHz处,相位噪声为-84.11 dBc/Hz,功耗为3.88 mW。     

MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6.91kHz/g.     

MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6 .91k Hz/g.     

一种低功耗全差分交叉耦合环形振荡器设计

提出了芯片内部振荡器的一种设计方案,该振荡器采用了全差分环形振荡器的结构,其延迟单元使用了共模反馈和交叉耦合晶体管对对频率进行调节校准,抑制相位噪声能力强。还提出了一种新型的基准源结构,这种结构产生的电流温漂系数小、电源抑制比高。该设计基于CSMC 0.35μm CMOS工艺,测试结果表明,在3.3V的低电源电压下,振荡频率抖动范围很小,中心频率在11.4MHz,功耗仅为1.4mW。     

一种低功耗低温漂振荡器的设计

基于0.15 μm BCD工艺,提出了一种低功耗低温漂振荡器。分析了环形振荡器的振荡频率温度漂移特性,采用翻转电平优化技术,结合短路电流控制技术,获得了低温度漂移的振荡频率。且电流消耗极低。该振荡器适用于锂电池保护监测芯片。测试结果表明,在-40 ℃~100 ℃温度范围、32 kHz振荡频率、5 V电源电压条件下,该振荡器的振荡频率随温度的变化率小于3.3%,电流消耗仅为170 nA。     

1种用于TPMS的新型环振式数字压力传感器

研制了一种新型环振式数字压力传感器,它可应用于汽车轮胎压力监测报警系统(TPMS).采用硅薄膜上的PMOS环形振荡器作为压力敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、温度系数低、灵敏度高以及制作工艺简单等特点.分析并设计了压力传感器的环形振荡器电路、混频器电路、物理结构.分析了环形振荡器的频率特性、环形振荡器的谐振频率与压力的关系,以及制作工艺,并制作了样品,其灵敏度为5.12 kHz/Bar.     

一种工艺和温度自校正的环形振荡器

提出了一种具有工艺和温度自校正功能的环形振荡器。相较于传统的环形振荡器,该环形振荡器增加了温度校正模块和工艺校正模块。当工艺角变化为ss→tt→ff,工艺校正模块会相应地调整延迟单元的供电电压,校正由工艺角引起的振荡频率变化。当温度在-40 ℃～125 ℃范围内变化时,温度校正模块为延迟单元提供一个与温度无关的电流,以稳定振荡频率。该环形振荡器采用GF 0.18 μm CMOS工艺进行设计,版图面积为(745×595)μm²。后仿真结果表明,当工艺角变化为ss→tt→ff,振荡频率的最大变化范围为1.27 MHz;当温度变化为-40 ℃～125 ℃,振荡频率的最大变化范围为0.199 MHz。     

全集成片上低温漂振荡电路

设计了一个全集成低温漂振荡电路,该电路通过将片上环形振荡器产生的振荡信号的频率转换为电压,并与片上基准电压源产生的基准电压进行比较,产生振荡器控制电压,实现稳定振荡器工作频率的目的.由于片上基准电压源和频率-电压转换电路具有较小的温度系数,振荡器的工作频率也具有较小的温度系数(140 ppm/℃).该电路无需从片外接收任何基准信号.另外,该设计具有对振荡器工作频率的负反馈调整机制,与单独的振荡器相比,输出信号的频率更加稳定,在0～100 ℃范围内,输出信号频率的变化小于1.35%.     

一种实用的电压控制环形振荡器

本文介绍了两种在集成电路中得到广泛应用的、作为内部时钟源的环形振荡器：RC环形振荡器和电压控制环形振荡器，并对引起振荡频率变化的关键因素进行了分析。     

一种实用的电压控制环形振荡器

本文介绍了两种在集成电路中得到广泛应用的，作为内部时钟源的环形振荡器，RC环形振荡器和电压控制环形振荡器，并对引起振荡频率变化的关键因素进行了分析。     

一种伪差分两级环形振荡器的设计

设计了一种伪差分两级环形振荡器,可为锁相环提供8 GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65 nm CMOS工艺进行设计与仿真。结果表明,在1.2 V电压下,振荡器的功耗为6.9 mW,1 MHz频率处的相位噪声为－82.104 5 dB,满足高速SerDes接口的设计要求。     

一种基于SiGe工艺的ECL环形振荡器

介绍了一种基于SiGe平面集成电路工艺制作的ECL环形振荡器,采用15级反相器闭环结构,能够产生280 MHz高频振荡信号,振荡周期为3.58 ns,平均每级反相器延迟为119 ps。该电路结构简单、易集成、成本低,可广泛移植于各类片上系统,用作时钟信号源等。     

利用震荡环频率特性提取多位可靠信息熵的物理不可克隆函数研究

针对传统物理不可克隆函数(PUF)产生信息熵少、易受环境因素干扰等问题,该文设计一种产生多位稳定信息熵的PUF方案。该方案通过对FPGA上环形震荡器所产生频率数据的分析,从每个震荡环中提取能够代表震荡环特性的特征位作为信息熵。通过对逆变器温度特性的研究,利用电流饥饿逆变器和常规逆变器组成新的震荡环来降低温度对产生的信息熵的可靠性的影响。通过Cadence IC仿真和进行赛灵思zynq 7000系列FPGA开发平台上的实验,结果表明改进的PUF结构使用相同数量的震荡环产生更多的信息熵,并且其可靠性、唯一性均得到提升。     

A run-time built-in approach of TID test in SRAM based FPGAs

Run-time TID test in SRAM based FPGAs can improve reliability in space applications, but none feasible approach has been presented. This paper proposes a lightweight built-in test approach, in which the propagation delay of combinational logic in FPGA is measured with ring oscillator in runtime. The differences between propagation delays in different time slots are provided as the metric of TID degradation. The irradiation experiments on Xilinx Zynq chip prove the validity of the proposed method.     

A mechanism for detecting on-chip radio frequency interference of field-programmable gate array

One-chip measurements without modifying the physical structure of packaged integrated circuits such as field-programmable gate arrays (FPGA) is challenging. This paper proposes a sensor for detecting the radio frequency interference (RFI) on the supply inside the FPGA chip. The core of the sensor is a ring oscillator built with FPGA look-up tables. The paper proposes a model to predict the response of the ring oscillator to power supply RFI, and shows that the normalized frequency shift of the ring oscillator resulting from the interference is determined by the amplitude of the interference. This relationship is independent of the interference frequency and the size of the ring oscillator. To verify the model, simulations on transistor-level look-up tables of 130-nm and 40-nm technologies were performed. The simulation results matched well with the model. In addition to simulation, an FPGA test board was fabricated. Measurements of FPGA RFI response were performed and the results were consistent with the theoretical model. The effect of the interference on the ring oscillator provided a mechanism to detect the amplitude of the supply interference on the FPGA chip. The frequency of the ring oscillator was monitored through the supply pin by measuring the spectrum of the supply noise. The properties of the sensor, such as constant response in a wide frequency range, insensitiveness to the oscillator size, ease of implementation, and minimal modification requirement of the physical structure, made it suitable for performing on-chip FPGA measurements.     

Flip-flop resolving time test circuit

Integrated circuit flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flip-flop to be measured. The circuit has five digital inputs, five digital outputs, including one for frequency measurements, and two analog inputs plus power and ground connections. Several delays that are fabricated as part of the test circuit, including a voltage controlled delay with a few picosecond resolution, are calibrated as part of the test procedure by grating them into and out of the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted, from the period of the ring oscillator with the delay included. A frequency divider is fabricated as part of the test structure to reduce the output of the ring oscillator to less than 200 kHz so no high-frequency inputs of outputs from the IC are required.     

A novel high-speed ring oscillator for multiphase clock generationusing negative skewed delay scheme

A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches     

High Effective Subharmonic Injection Locking of a Millimeter-Wave IMPATT Oscillator

Abstract-Effective stabilization of an IMPATT oscillator in the millimeter-wave region can be achieved through subharmonic injection locking to a weak parasitic oscillating signaI. In subharmonic injection-Iocking experiments more than 19 dB of locking gain at 10-MHz locking range was obtained at a subharmonic ratio 1:2 of the main oscillating frequency. At the subharmonics 1:4 and 1:6, the locking gain was more than 12 and 13 dB at 10 MHz, respectively. Using the parasitic oscillating signal, higher than 32-dB gain and 10-MHz locking range at a subharmonic ratio 1:2 of the parasitic oscillating frequency was obtained. This locking gain was 13 dB higher than that for the main oscillating signal. At the subharmonic ratio 1:4, the gain was more than 15 dB higher. As measured with the spectrum analyzer, the oscillating signal which was locked by the subharmonic injection signal almost coincided with the injection signal. These data show that the subharmonic injection locking has high gain as compared with that using the main oscillating signal.     

SOI CMOS器件研究

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。     

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.