基于改进陷阱模型的新型p型隔离层结合场板结构的4H-SiC MESFET的特性研究与优化

本文提出了一种致力于抑制表面陷阱影响的新型结构。基于能准确表征4H-SiC材料特性的物理模型和经过实验证明能较好表征表面陷阱作用机理的模型,对器件的特性进行了研究。通过与实际器件制作中主流采用的埋栅-场板结构的4H-SiC MESFET以及实验测试的器件特性的对比,本文提出的结构在整体上对器件的特性有所提高 。新结构引入的 p型隔离层能有效地抑制表面陷阱的影响并且能减小器件在大电压微波应用条件下的栅漏电容;P型隔离层结合场板结构改善了栅极边缘的电场分布,同时能减小单一使用场板结构时场板对沟道引入的附加栅漏电容; 作为微波晶体管,由于更好的抑制了表面陷阱,基于本文提出的结构的4H-SiC MESFET比埋栅-场板结构的器件具有更高的栅延迟抑制比;在实现大功率应用方面,新型结构同样能提供更高的耐压。新结构的4H-SiC MESFET的最大饱和漏电流密度为460mA/mm,在漏电压20V的栅延迟抑制比接近90%。交流特性的分析结果表明,本文提出的结构比埋栅-场板结构的器件的特征频率和最高振荡频率分别高出5%和17.8%。此外,新结构的器件能承受较高的击穿电压,进而保证了器件的大功率密度。针对本文提出的结构进行了优化,以使器件能发挥最好的微波特性并对器件的设计提供一定参考。     

沟槽阻挡型阳极结构门极换流晶闸管特性研究

引入沟槽结构,提出一种改进型注入效率可控门极换流晶闸管。新结构采用沟槽型阻挡结构代替阳极表面平面型氧化薄层,实现对基区漂移电子阻挡和积累作用,保持了注入效率自调整效应,减小了平面型氧化阻挡层对阳极有效面积的影响。模拟结果表明,新结构器件实现了注入效率控制功能,增大了有效阳极接触面积并降低了通态压降;其沟槽宽度可调节注入效率和关断特性。     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

具有浮空埋层的高压器件新结构和击穿电压模型

提出具有浮空埋层的变掺杂高压器件新结构(BVLD:Variation in lateral doping with floating buriedlayer),建立其击穿电压模型.线性变掺杂漂移区的电场耦合作用使表面电场达到近似理想的均匀分布,n+浮空等电位层与衬底形成新平行平面结,使得纵向电压由常规结构的一个pn结承...     

Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification

A novel p-channel flash device with a SiGe layer is proposed, which is based on the analysis made with the simulator MEDICI, to enhance the band-to-band-tunneling current and improve the programming speed. The programming biases of the p-channel flash device can be reduced with an equal programming speed. Simulation results show that more than one hundred times enhancement in the programming speed or 35% reduction of the drain voltage can be achieved in the proposed p-channel flash device with a 40% Ge content in the surface SiGe layer. In addition, a Si-cap layer is inserted between the SiGe and the tunneling oxide to obtain a high-quality interface and to optimize the cell structure.     

A new poly-Si thin-film transistor with poly-Si/a-Si double activelayer

A new poly-Si TFT employing a rather thick poly-Si (400 Å)/a-Si(4000 Å) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved     

Optical characterization of diamond MIS capacitors

The transient photoresponse properties of diamond metal-insulator-semiconductor (MIS) capacitors have been characterized for the first time. Capacitors were fabricated on natural diamond using an electrochemical cleaning step with a CVD SiO₂ dielectric and an optional carbon implantation to create a nonuniform doping profile. Devices were found to function as integrating photodetectors and were evaluated by the spectral dependence of the transient photocapacitance (PC). We discuss a model that distinguishes between the responses due to inversion layer population and that due to bulk trap occupancy changes. Inversion charge generation was observed at all wavelengths investigated and it dominated the PC transient at photon energies above 3 eV. Possible reasons for this result are discussed and analyzed. We could not demonstrate a suitable way to use carbon implantation to form a surface n-type layer in a MIS device without degrading the device IV properties and eliminating the integrating photoresponse observed on non-implanted devices. These results suggest that diamond charge-storage devices can function only if the diamond surface is prepared properly before device fabrication     

非均匀厚度漂移区SOI高压器件及其优化设计

提出非均匀厚度漂移区SOl高压器件新结构及其优化设计方法.非均匀厚度漂移区调制SOI层的电场并增强埋层电场,从而 提高器件击穿电压.考虑到这种调制效应.提出解析模型用以优化设计该新器件的结构参数.借助解析模型,研究了电场分布和器件击穿电压与结构参数的关系.数值仿真'证实了解析模型的正确性.具有3阶梯的非均匀厚度漂移区SOl器件耐压为常规结构SOl器件的2倍,且保持较低的导通电阻.     

非均匀厚度漂移区SOI高压器件及其优化设计

提出非均匀厚度漂移区SOI高压器件新结构及其优化设计方法. 非均匀厚度漂移区调制SOI层的电场并增强埋层电场,从而提高器件击穿电压. 考虑到这种调制效应,提出解析模型用以优化设计该新器件的结构参数. 借助解析模型,研究了电场分布和器件击穿电压与结构参数的关系. 数值仿真证实了解析模型的正确性. 具有3阶梯的非均匀厚度漂移区SOI器件耐压为常规结构SOI器件的2倍,且保持较低的导通电阻.     

Numerical simulation of GaAs MESFETs with a p-buffer layer on asemi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current is reduced due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e. it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer     

Numerical analysis of kink effect in HJFET with a heterobufferlayer

The kink effect in an AlGaAs/GaAs HJFET with a heterobuffer layer is investigated using a two-dimensional device simulator with impact ionization and deep-trap models. It is confirmed that the accumulation of holes generated by impact ionization causes the kink effect. The influence of deep levels on the kink characteristics is also investigated. The kink effect is suppressed by electron traps in the channel region through the recombination of the generated holes. On the other hand, the kink effect is enhanced by hole traps, which are positively ionized by increases in hole concentration. However, excessive hole trap concentration suppresses the accumulation of holes, due to enhanced recombination with electrons. Under such conditions the kink effect vanishes     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

Super-High Breakdown Voltage (>1200V) SOI LDMOS with A Buried P-type Layer and A Thin BOX

为探索在薄埋氧层SOI衬底上实现超高耐压LDMOS的途径,提出了一种具有P埋层（BPL）的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1280V的耐压,将BOX层减薄到几百纳米以下又可以改善其热特性。     

以ZnO为空穴缓冲层的高效率有机电致发光器件

研制了在传统双层有机电致发光器件(OLED) ITO/NPB/AlQ/Al的阳极与空穴传输层间加入ZnO缓冲层的新型器件.研究了加入缓冲层后对OLED性能的影响,并比较了新型与传统OLED的性能,结果表明,新型器件比传统器件的耐压能力有了显著提高;当电压达到7 V时,发光效率提高了35%.分析认为,ZnO缓冲层的加入,改善了界面, 减少了漏电流,并且阻碍了空穴的注入,有利于改善空穴和电子的注入平衡,提高复合效率.     

一种提高ESD性能的高压SBD器件结构研究

提出了一种新型SBD器件结构,并应用于高压SBD产品的研制。该结构通过在肖特基势垒区的硅表面增加一层表面缓冲掺杂层(Improved Surface Buffer Dope),将高压SBD的击穿点从常规结构的PN结保护环区域转移到平坦的肖特基势垒区,从根本上提高了器件的反向静电放电(ESD)和浪涌冲击能力。经流片验证,采用该结构的10A150VSBD产品和10A200VSBD产品均通过了反向静电放电(HBM模式)8kV的考核,达到目前业界领先水平。该结构工艺实现简单,可以应用于100V以上SBD的批量生产。     

Magnetic resonance studies of GaN based light emitting diodes

We report the application of electrical detection of magnetic resonance (EDMR) and electroluminescence detection of magnetic resonance (ELDMR) to study the recombination processes in InGaN/AlGaN double heterostructure p-n junctions. These techniques are especially well suited to the problems of defects in device structures in that they are much more sensitive than conventional paramagnetic resonance and are responsive to only those defects involved in the electrooptical properties of the structure. One resonance is observed at g≈2.00 and is identified as a Zn-related acceptor trap in the InGaN layer. A second resonance with g≈1.99 is identified as a deep donor.     

复合埋层上的薄层SOI-LDMOS功率器件

为了提高SOI-LDMOS功率器件击穿电压及相关性能,针对薄层SOI-LDMOS功率器件提出了一种新结构,在新结构中引入了复合埋层,它由p埋层与Si3N4绝缘介质埋层构成。复合埋层不仅改善了比导通电阻与耐压的关系,而且还缓解了自热效应。仿真结果表明,在漂移区长度为57 m时,新结构耐压达到了1052 V,与CamSemiSOI相当,而比导通电阻与表面最高温度分别比CamSemi SOI降低了233.05.mm2和64 K。     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

微机械自润滑材料的摩擦性能研究

研究了Ni-MoS2自润滑层在不同工艺条件下的结构特征、形貌，并分析其摩擦特性，发现润滑层表面粗糙度和厚度对摩察系数影响较大；即使MoS2含量较少，Ni-MoS2复合镀层的极限剪切模量也比金属Ni降低很多。这为LIGA技术制造自润滑MEMS器件提供了有益的参考，并提供低MoS2含量的Ni-MoS2复合材料的一些基本性质。     

AlGaN/GaN HEMT device reliability and degradation evolution: Importance of diffusion processes

A methodology based on combined electrical trapping analysis with UV-assisted preparation of trap states and electroluminescence analysis was developed to gain detailed understanding of trap generation in AlGaN/GaN HEMTs during off and on-state stress. This is used to identify electronic trap location laterally and vertically in a device structure and the nature of the degradation mechanism. We identify the generation of traps with activation energies in the range from 0.45 to 0.65 eV near the gate edge on its drain side in AlGaN/GaN HEMTs as electronic traps in the AlGaN device layer, as a result of on- and off-state stress. Degradation studied on devices subjected to stress under different backplate temperatures, points to diffusion processes playing an important role for early device degradation. Diffusion constants showed thermal activation energies of ∼0.26 eV consistent with diffusion processes along dislocations, with possible additional contributions from bulk diffusion accelerated by converse/inverse piezo-electric strain and leakage currents.