四种级联差分相位调制码的100 Gbit/s传输

在级联相位调制的100 Gbit/s光信号传输系统中,对差分相移键控非归零码(NRZ-DPSK)、差分相移键控归零码(RZ-DPSK)、差分四相相移键控非归零码(NRZ-DQPSK)和差分四相相移键控归零码(RZ-DQPSK)进行了比较研究.当四种信号通过90 km的标准单模光纤(SMF)和16 km的色散补偿光纤(DCF)传输后,在满足相同入纤功率的条件下,NRZ-DQPSK信号具有最高的色散容限;如果仪仪考虑一阶偏振模色散(PMD),RZ-DQPSK信号具有最优的抗偏振模色散特性;当入纤功率在O～10 dBm的范围内凋节时,RZ-DPSK信号具有最好的非线性容忍度;最后比较了四种相位调制码型传输后通过不同带宽的三阶高斯滤波器后的接收性能,得出滤波器带宽值大于125 GHz后,NRZ-DPSK信号的接收性能最佳.     

100 Gbit/s级联交错相位调制码型信号的传输性能

介绍了一种应用于100 Gbit/s传输系统的新型光信号调制码型--交错差分相位调制码(SDPSK).该码型的解调仅通过一个1 bit延时的马赫曾德尔延时干涉仪和一个平衡接收机即可实现.与传统的4种级联相位调制码型进行长距离传输特性比较后证明:基于NRZ码和50%占空比RZ码的SDPSK码与相同包络的DPSK码具有几乎相同的色散容限和一阶偏振模色散容限;与有相同包络的DPSK信号和差分四相相移键控码(DQPSK)信号相比,基于NRZ码和RZ码的SDPSK信号具有更高的抵抗非线性负面效应的能力:经过90 km普通单模光纤传输并采用16 km色散补偿光纤进行后置色散补偿后,通过带宽值大于125 GHz的三阶高斯滤波器检测光信号,RZ-SDPSK信号的接收性能最佳.     

NRZ码和CSRZ码在40 Gbit/s单通道系统中传输性能分析

文章仿真了非归零码(NRZ)和载波抑制归零码(CSRZ)在40 Gbit/s单通道系统中G.652光纤上传输6×80 km的性能.比较了两种码型对接收端光滤波器和电滤波器带宽的要求、不同的入纤功率下功率代价以及残余色散对比.结果表明,在高速传输系统中,CSRZ码的传输性能明显优于NRZ码.     

40Gb/s DWDM系统不同码型传输性能的比较

采用Optisystem软件,对比分析了非归零码(NRZ)、归零码(RZ)、载波抑制归零码(CS-RZ)和载波抑制归零差分相移键控码(CSRZ-DPSK)四种码型在8×40Gb/s DWDM系统的传输性能。结果表明,CSRZ-DPSK码抗色度色散和PMD性能最优,CS-RZ码的OSNR容限最低。当入纤光功率适中、色散和色散斜率同时补偿时,CSRZ-DPSK码和CS-RZ码的最大传输距离超过2700km。     

40Gb/s光纤通信系统中不同码型传输特性的实验研究

在高速光纤通信系统中码型的选择是决定系统传输质量和光谱效率的主要因素。码型的选择和信道速率、信道波长间隔、光放大器的选择、光放大器放置间隔、光纤的类型、色散管理策略等各种因素密切相关。分析了非归零码（NRZ）、归零码（RZ）和载波抑制归零码（CSRZ）码型的产生方式及特点。采用单信道和掺铒光纤放大器（EDFA）放大方式对三种码型进行了40Gb/s的100kmG.652光纤通信传输实验。比较了三种码型的系统传输持性、最佳入纤功率和不同入纤功率下的功率代价：载波抑制归零码最佳入纤功率为9dBm，功率代价小于非归零码和归零码。结果表明，在相同的色散补偿条件下，载波抑制归零码比归零码和非归零码有更优的非线性容忍度。     

RZ、CSRZ码在CBG色散补偿系统中的传输

全部利用线性啁啾光纤布拉格光栅（CBG）作色散补偿模块和在线通道滤波顺，在2500km超长距离的G．652光纤上实现10Ghps归零码（RZ）、载波抑制归零码（CSRZ）光信号的无电中继传输，并在2080km和2560km处分别对2种信号的传输性能进行了测试。CSRZ在上述2处的功率代价分别为～1dBm和～3dBm（BER-10^12，PRBS=10^23-1），RZ的功率代价分别为～3dBm和～5dBm，验证了在相同系统平台下CSRZ光信号比RZ光信号有更好的性能.     

改进型双二进制归零码信号在标记交换系统中的新应用

提出以改进型双二进制归零码(MD-RZ)信号作为标记,分别采用差分相移键控非归零码(NRZ-DPSK)信号和差分正交相移键控非归零码(NRZ-DQPSK)信号作为载荷进行正交调制的新方案.然后提出了一种从标记信号中提取和恢复时钟的简单方案.比较了背对背系统中2.5 Gbit/s的MD-RZ标记叠加到10 Gbit/s的NRZ-DPSK载荷和20 Gbit/s的NRZ-DQPSK载荷上的频谱特性,证明了MD-RZ标记占空比越大,光分组信号的频带利用率越高.采用传统的二进制强度调制-直接检测(IM-DD)系统的接收机检测得到了背对背系统中不同占空比的2.5 Gbit/s MD-RZ标记的眼图.结果表明,若采用色散补偿技术,两种光分组信号中的MD-RZ标记能够在长距离传输时克服接收端眼图的失真;当入纤功率值高于18 dBm时,占空比取值越大,MD-RZ标记的眼开度代价具有越高的传输鲁棒性.     

基于HNLF的RZ到NRZ的全光码型转换

数值仿真分析了利用高非线性光纤(HNLF)的交叉相位调制(XPM)效应实现归零(RZ)码到非归零(NRZ)码的转换,并讨论了RZ信号占空比、光纤色散对转换后NRZ信号Q因子的影响.数值结果表明:转换后NRZ码的Q值受输入RZ信号占空比的影响;而且RZ信号与连续的探测光之间的色散差也严重影响转换后NRZ信号的Q因子值.     

40Gb/sWDM系统中RZ&NRZ调制格式的性能比较

利用数值计算的方法对40G WDM系统进行了仿真.在考虑了光纤群速度色散(GVD)、三阶色散(TOD)、自相位调制(SPM)、交叉相位调制(XPM)、四波混频(FWM)和偏振模色散(PMD)的前提下,通过对比眼图和Q因子,对归零码(RZ)和非归零码(NRZ)调制格式的传输性能进行了研究.     

基于光纤差分相移键控的色散补偿方案的研究

为了研究光差分相移键控(DPSK)调制格式在光纤高速传输系统中的色散补偿, 利用色散补偿光纤(DCF)的色散补偿原理, 对40Gbit/s光纤传输系统进行色散补偿, 分析了40Gbit/s单通道光纤传输系统中3种DPSK调制格式信号的频谱特性; 仿真了3种码型的色散容忍度以及3种调制格式在考虑光纤的非线性下的色散补偿方案。结果表明, 光非归零码差分相移键控(NRZ-DPSK)信号具有最好的色散容忍度, 但其受非线性的影响比较大; 33%归零码差分相移键控(33%RZ-DPSK)信号的色散容忍度差, 但其色散补偿后的效果优于NRZ-DPSK; 而载波抑制归零码差分相移键控信号对色散和非线性效应都有较好的抑制; 3种DPSK调制格式均在对称补偿2方案中色散补偿的效果最佳。此仿真研究对光DPSK信号在光纤中的色散补偿具有参考意义。     

High-power pulsed GaAs double-drift hybrid-read impatt diodes for X-band

Gallium-arsenide double-drift hybrid-Read Impatt diodes have been developed to deliver high peak and average powers in X-band. A peak power output of 35 W with 20% efficiency has been obtained at 8.3 GHz for 20% duty cycle. Peak power output of 32 W with 20% efficiency has been obtained at 8·6 GHz for a 25% duty cycle. Peak power output of 26 W with 21.5% efficiency has been obtained at 8.6. GHz for 33% duty cycle.     

ASMD with duty cycle correction scheme for high-speed DRAM

An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range     

Wavelength re-generation and re-modulation using optical phase lock loop techniques for 100-Gb/s DQPSK up-stream transmission in DWDM passive optical networks

We demonstrate, by partial experiment and simulation, a re-modulation scheme of the lightwave carrier imbedded in a downstream optical signals under differential quadrature phase shift keying (DQPSK) modulation format for upstream transmission over passive optical networks (PONs) at a bit rate of 100 Gb/s. The recovery of the optical carrier with the precise wavelength is implemented using an injection laser incorporating an optical phase locked loop (OPLL). In the computer simulation, the OPLL is implemented by a Simulink model consisting of interconnected system blocks following exactly the physical phenomena of the hardware structures. This model is then integrated with DQPSK modulation formats for up- and down-transmissions in PONs. Pulse shaping of Non-Return-to-Zero and Return-to-Zero (RZ) of 50% duty cycle and 67% duty cycle are used, respectively. Dispersion tolerance of 25 ps/nm with a bit error rate (BER) of 10⁻⁹ is achieved for both down- and upstream transmissions over fully dispersion compensated 80- km standard SMF and 1.5- km SSMF equivalent dispersion with carrier suppressed RZ pulse shaping (CS-RZ 67%). The contribution to BER by the timing synchronization error at the sampling of the optical network unit for re-modulation and related power penalty of these modulation formats is also investigated. It is noted that using the optical phase locking technique it is possible to remove any cross talks which may be generated from nonlinear effects such as cross-phase modulation, self-phase modulation, and four wave mixing.     

An Energy-Efficient Self-Adaptive Duty Cycle MAC Protocol for Traffic-Dynamic Wireless Sensor Networks

A plenty of Medium Access Control (MAC) protocols deal with static traffics with low traffic load. The performance of these protocols drops significantly when network traffic become dynamic or in high traffic load. In this paper, we propose a new MAC protocol called Self-Adaptive Duty Cycle MAC (SEA-MAC) by introducing dual adaptive mechanisms: (1) An Adaptive Scheduling (AS) mechanism which makes the nodes’ active duration adaptive to variable traffic load, thus enabling SEA-MAC to resiliently schedule data transmission for the Sleep period. The algorithm is designated to schedule more data transmission in bursty and high traffic load, thus enabling rapid dissemination of data and reduction of latency. While under the light traffic load, nodes enter the Sleep mode timely, mitigating idle listening and saving energy. (2) A Self-Adaptive duty cycle mechanism which further adjusts the duty cycle and makes SEA-MAC adaptive to the dynamic traffic loads. When network experience with very low or very high traffic load, the protocol further adjusts duty cycle dynamically based on the traffic load, thus reducing inefficient duty cycle or reduce end-to-end delay. Experiment results show that the SEA-MAC is a great advancement compared with AS-MAC and RI-MAC protocols on the performance for unicast scenarios, especially under heavy unicast traffic load. SEA-MAC can reduce average and max end-to-end delay up to 50.90 and 68.20% respectively, lower energy consumption up to about 16.28%, and increase PDR up to about 16% compared with AS-MAC. SEA-MAC superiors to RI-MAC in average end-to-end delay by up to 80% and in maximum end-to-end delay up to 90% for all the traffic load in question. SEA-MAC outperforms RI-MAC significantly in average duty cycle under medium and heavy traffic load.     

光MDPSK通用调制解调结构构建及仿真

新型相位调制格式技术能够有效地减少光传输损伤,是光传输系统中的重要技术。从理论上分析了光MDPSK(M进制差分相移键控)的调制解调原理,构建了通用的调制解调结构,并首次推导出MDPSK的通式和解调公式,最后以基于CSRZ(载波抑制归零,占空比为67%)码的DQPSK(差分正交相移键控)、8DPSK(3阶差分相移键控)和16DPSK(4阶差分相移键控)为例,用MATLAB软件仿真得到了其调制后的频谱图和解调后的眼图。仿真结果表明,随着级数的增加,MDPSK调制格式的频谱宽度会逐渐变窄,且解调后的眼图也令人满意。     

Effect of Duty Cycle on Properties of Pulse-electro-deposited SnS:Ag Thin Films

SnS∶Ag thin films were deposited on ITO glasses by pulse electro-deposition. By studying the effect of duty cycle on the properties of SnS∶Ag thin films, the optimum off-time(toff) is obtained to be 5 s, namely, the optimal duty cycle is about 67%. The primary phase of SnS∶Ag films deposited on optimum parameters condition is SnS compound with good crystallization, and the films prefer to grow towards (111) plane. The films are dense, smooth and uniform with good microstructure, and the grains in the films are densely packed together, and their direct bandgap is about 1.40 eV. In addition, the bandgap of the films first rises and then drops with the increase of the duty cycle.     

偏振相关损耗对偏振模色散补偿系统性能的影响

数值分析了40Gb／s占空比50％的归零码（RZ）、占空比38％的RZ和载波抑制归零码（CSRZ）3种不同码型系统中偏振相关损耗（PDL）对偏振模色散（PMD）补偿的性能，并和不考虑PDL的情况作了比较。结果表明，由于PDL的存在，导致补偿系统的补偿性能恶化严重，使得损耗概率增加，眼图张开度减小；3种码型中，CSRZ码型系统的缓解性能比其他两种码型要好。     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

MCRB for timing,phase and frequency estimation in presence of self-phase modulation for low-rate optical communication

In this paper we derive the theoretical lower bound, namely Modified Cramér-Rao bound (MCRB) for symbol timing, phase and frequency offset in presence of nonlinear self-phase modulation (SPM) in a dispersion compensated long-haul coherent fiber link. The system model considers multiple span of fiber each associated with optical amplifier. Dual polarization multilevel quadrature amplitude modulation is opted for data transmission to support the data rate lower than 10 Gigabaud. We find that SPM induces underdamped oscillation on the MCRB bounds depending on the pulse shapes (symmetric and asymmetric) utilized. In presence of realistic low-pass filter at the receiver front end, the MCRB degrades significantly due to SPM. We also show the effect of SPM on symbol error rate degradation. Simulation is carried out with symmetric return-to-zero pulse with duty cycles of 33, 67 % and self-generated asymmetric pulse to verify the theoretical results.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.