采用源极增强带带隧穿热电子注入编程的新型p沟选择分裂位线NOR快闪存贮器

提出一种新型的PMOS选择分裂位线NOR结构快闪存贮器,具有高编程速度、低编程电压、低功耗、高访问速度和高可靠性等优点.该结构采用源极增强带带隧穿热电子注入进行编程,当子位线宽度为128位时,位线漏电只有3.5μA左右,每位编程功耗为16.5μW,注入系数为4×10-4,编程速度可达20μs,存贮管的读电流可达60μA/μm以上.分裂位线结构和低编程电压使得该结构具有很好的抗位线串扰特性和可靠性.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

一种感应PN结隧穿场效应晶体管

提出了一种在源区形成感应PN结的隧穿场效应晶体管,利用Silvaco TCAD对器件的工作原理进行了验证,并仿真分析了器件的静态电学特性以及动态特性。结果表明,这种结构的TFET具有低的亚阈值斜率(51mV/dec.)、高的开态电流(5.88μA/μm)、高的开/关态电流比(ION/IOFF为107)以及低至9ps的本征延迟时间,表明利用该结构的TFET器件有望构成高速低功耗逻辑单元。     

一种高速只读存储器拓扑结构的设计

随着只读存储器密度越来越大,对读取速度的要求越来越高,位线大电容逐渐成为影响只读存储器读取速度的关键问题.设计了一种存储器拓扑结构,这种结构通过改变存储单元读取点的位置,能有效避免位线大电容充放电对读取速度的不利影响,极大地缩短了读取周期,提高了只读存储器的读取速度.该拓扑结构的优势在TSMC 0.13μm工艺仿真库里得到验证.     

电荷泵法研究FLASH擦工作时带带隧穿引起的界面损伤

FLASH在擦操作的过程中,带带隧穿产生的空穴注入将会在SiO2/SiO2界面和氧化层中产生带电中心(包括界面态和陷阱),影响电路的可靠性.利用电荷泵方法,通过应力前后电荷泵电流的改变确定出界面态和陷阱电荷的空间分布,为FLASH单元设计与改进可靠性,提供了理论和实验基础.     

电荷泵法研究FLASH擦工作时带带隧穿引起的界面损伤

FL ASH在擦操作的过程中 ,带带隧穿产生的空穴注入将会在 Si O2 / Si O2 界面和氧化层中产生带电中心 (包括界面态和陷阱 ) ,影响电路的可靠性 .利用电荷泵方法 ,通过应力前后电荷泵电流的改变确定出界面态和陷阱电荷的空间分布 ,为 FL ASH单元设计与改进可靠性 ,提供了理论和实验基础     

一种高PSR CMOS带隙基准电路设计

为了降低芯片电路功耗,电源电压需要不断的减小,这将导致电源噪声对基准电压产生严重影响。为此针对这一问题进行相关研究,采用SMIC 0.18μm工艺,设计出一种低功耗、低温度系数的高PSR带隙基准电压源。仿真结果表明,该设计带隙基准源的PSR在50 kHz与100 kHz分别为-65.13 dB和-53.85 dB;在2⁶ V电源电压下,工作电流为30μA,温度系数为30.38 ppm/℃,电压调整率为71.47μV/V。该带隙基准适用于在低功耗高PSR性能需求的LDOs电路中应用。     

一种高性能CMOS带隙电压基准源设计

采用一级温度补偿和电阻二次分压技术设计了一种高性能CMOS带隙电压基准源电路,其输出电压为0.20～1.25V,温度系数为2.5×10-5/K.该带隙电压基准源电路中的深度负反馈运算放大器为低失调、高增益的折叠型共源共栅运算放大器.采用Hspice进行了运算放大器和带隙电压基准源的电路仿真,用TSMC 0.35μm CMOS工艺实现的带隙基准源的版图面积为645μm×196μm.     

一种新型指数补偿BICMOS带隙基准源

在分析了带隙基准的指数曲率补偿原理的基础上,设计了一个低功耗、低温度系数、高电源抑制比的新型BICMOS带隙基准源电路.该电路基于0.6μm BICMOS工艺进行设计、仿真和实现.仿真结果表明,该带隙基准源在5V电源电压下,电源电流为50μA;温度变化范围从-40℃～110℃时,温度系数为2ppm/℃;低频电源抑制比为-105dB;负载从空载到驱动1k电阻时调整率为0.6mV.     

Program load adaptive voltage generator for flash memories

This paper describes a program load voltage generator for flash memories. It is based on an adaptive feedback loop which senses the current delivered to the memory cells during programming and adjusts the output voltage accordingly to compensate for the voltage drop caused by the programming current across the bit-line select transistors. The proposed circuit (silicon area=0.065 mm²) was integrated in a 0.8-μm CMOS 4 Mb flash memory device (0.6 μm in the matrix). Experimental evaluations showed that very effective compensation is achieved, with bit-line voltage kept at the desired value during the whole programming operation. A spread as small as 70 mV was measured between the single-bit and 16-b programming cases     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

A Low-Power SRAM Using Bit-Line Charge-Recycling

Low-power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. Reducing voltage swing of the bit-line is an effective way to save the power dissipation in write cycles. Voltage swing reduction of bit-lines is, however, limited due to possible write-failures. We propose a new low-power SRAM using bit-line charge recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance, instead of the power line. Applying such a charge recycling technique to the bit-line significantly reduces write power. A test chip with 32 Kbits (256 rows x 128 columns) is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the proposed SRAM. Measurement results show 88% reduction in total power during write cycles compared to the conventional SRAM (CON-SRAM) at V_DD = 1.5 V and f = 100 MHz.     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport

We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an $ hbox{n}^{+}$ BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a $V_{rm ds}$ of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.      

A current direction sense technique for multiport SRAM's

This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme