A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.     

一种应用于串行链路的5Gb/s低功耗电流模预加重发送器

A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode(VM) and current mode(CM) output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm~2.     

Design of a transversal equalizer for electronic dispersion compensation in optical communication links

A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps,which ensure that the equalizer can work at the bit rate of 10 Gb/s.With different tap gains,the forward voltage gain of the transversal equalizer varies,which demonstrates that the equalizer has various filtering characteristics such as low pass filtering,band pass filtering,band reject filtering,and notch filtering,so it can effectively simulate the inverse transfer function of dispersive channels in optical communications,and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion.The equalizer(including pads) occupies an area of 0.40 mm × 1.08 mm,and its total power dissipation is 400 mW with 3.3 V power supply.     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

Photoluminescence properties of solid-state Tb3+ doped NaY(MoO4)2

A cost-effective ultra-dense wavelength-division-multiplexed passive optical network（UD-WDM PON） with speed of 12.5 Gbit/s and channel spacing of 12.5 GHz is proposed and demonstrated. The distributed feedback（DFB） lasers modulated in 4-level pulse amplitude modulation（4-PAM） format are used for downstream links, and the reflective semiconductor optical amplifiers（RSOAs） together with an optical frequency comb modulated in quadrature phase shift keying（QPSK） format are used for upstream links. We can achieve the error-free transmission of the upstream signals with speed of 12.5 Gbit/s even after 20 km single-mode fiber（SMF）. The power penalty obtained by using the frequency comb generator instead of a tunable laser is around 0.5 d B. By using 11 DFB lasers and a set of intensity and phase modulators, it is possible to provide the seed light for 297 optical network units（ONUs） within the C-band.     

应用于数字和模拟光通信的高速电吸收光调制器

An electro-absorption （EA） modulator is one of key components for optical fiber communications due to the high speed, small size, low voltage and integration ability with other semiconductor devices. A 40 Gb/s InGaAsP/InP multiple-quantum-well （MQW） EA modulator monolithically integrated with a semiconductor optical amplifier （SOA） was fabricated for digital communications. The modulator capacitance was reduced to obtain 40 GHz bandwidth, and the SOA section helped reduce the insertion loss from 18 dB to 3 dB. InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications. A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz^2/3 were estimated by static and dynamic measurements.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μm~2.Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps.At a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.     

Design of BLDCM Driving and Control System for Motorized Treadmill

To satisfy the requirement of developing a new generation of motorized treadmill for a famous domestic manufacturer, a brushless DC motor （BLDCM） driving and control system for motorized treadmill is developed. High integration and reliability of this system are ensured under the condition that intelligent power module （IPM） is used and the protection module is included. Periodic current control method is applied to reduce the average current flowing through the armature winding of the motor when the treadmill is required to start with low speed while large load is added. Piecewise proportion-integration-differentiation （PID） control algorithm is applied to solve the problem of speed fluctuation when impulse load is added. The motorized treadmill of a new generation with the driving and control system has the advantages of high reliability, good speed stability, wide timing scope, low cost, and long life-span. And it is very promising for practical applications.     

Selected area growth integrated wavelength converter based on PD-EAM optical logic gate

A selected area growth wavelength converter based on a PD-EAM optical logic gate for WDM application is presented, integrating an EML transmitter and a SOA-PD receiver. The design, fabrication, and DC characters were analyzed. A 2 Gb/s NRZ signal based on the C-band wavelength converted to 1555 nm with the highest extinction ratio of 7 dB was achieved and wavelength converted eye diagrams with eyes opened were presented.     

一种10Gb/s具有周期性相位校准双沿触发CDR和CTLE/DFE组合均衡功能的接收端

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.     

Concurrent Blind Channel Equalization in Impulsive Noise Environments

In some communication systems the trans- mitted signal is contaminated by impulsive noise with a non-Gaussian distribution. Non-Gaussian noise caused significant performance degradation to communication re- ceivers. The new constant modulus blind equalizer based on Fractional lower-order statistics of the equalizer input, which is defined as FLOS_CMA, is able to mitigate impul- sive channel noise while restoring the constant modulus character of the transmitted communication signal. How- ever, like the Constant modulus algorithm （CMA）, the steady-state Mean square error （]VISE） of the FLOS_CMA algorithm may not be sufficient low for the system to ob- tain adequate performance. This paper proposes a con- current equalizer, in which a Decision-directed least mean p norm （DD_LMP） equalizer operates cooperatively with a FLOS_CMA equalizer, controlled through a non-linear link. Simulation results using M-QAM and 8-PSK signal- ing have shown that besides the capability of compensating the phase offset, the proposed concurrent FLOS_CMA and DD_LMP blind equalizer has faster convergence rate and lower steady-state MSE than the FLOS_CMA approach.     

一种具有快速电压跟随和宽输出电压范围的电压模式DC-DC降压型变换器

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed and wide output voltage range has been proposed. A novel error amplifier （EA） is presented to achieve a high DC gain and get high phase margin, including a resistor and capacitor net, a unit gain block and a high gain block. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 6 MHz with the output voltage range from 0.6 to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs while the load current suddenly changes 400 mA.     

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

A new loading-balanced architecture for high speed and low power consumption pipeline analog-to-digital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system''s point of view, all load capacitors of the shared OTAs are balanced by employing a loading-balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm². The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 mW at 200 MS/s from a 1.8 V supply.     

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications.     

A Homotopy—Controlled Mean Field Annealing Partially—Connected Neural Equalizer for Pan—European GSM Syst5em

Channel equalization is essential in the Pan-European GSM mobile communication system.The maximum likelihood sequence estimation(MLSE) using the Viterbi algorithm(VA)iscommonly recommended for the dqualization,which can only accommodate the channels with limited time delay spread.In[1],we presented a mean field annealing(MFA)partially connected neural equalizer for the GSM system,in which the complexity is linearly proportional to the time delay spread and therefore relatively fast convergence speed is achieved.But the annealing coefficient of the MFA equalizer is fixed,which is not flexible in timing-varying circumstance such as mobile communications.To decrease the computation of MFA approach so as to make it more easy for practical use,the MFA approach is reated as a homotopy problem.The ordinary equations which the MFA approach should obey are derived.These equations can be used to reflect the deviation of the iteration result from the track of MFA approach.Based on this tesult,an adaptive annealing control algorithm is proposed,which can dynamically control the annealing coefficient according to the iteration deviation.Computer simulations show that our approach can provide a much higher convergence speed and performance improvement over 16-state and 32-state VA‘s which are usually suggested for practical applications.     

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2 including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.     

应用于CMOS图像传感器中带有失调电压消除功能的电容比值非相关十位循环式模数转换器

A 10-bit ratio-independent switch-capacitor（SC） cyclic analog-to-digital converter（ADC） with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio（SNDR） of 53.6 dB and a DNL of C0：12/0：14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.     

8 × 10 Gb/s transmission system over 2 015 km with dispersion compensation by fiber Bragg Grating

The cascaded chirp fiber Bragg gratings（CFBGs） with ITU-T standard wavelengths and wavelength grid are applied to compensate the dispersion of 8×10 Gb/s WDM system. The ASE of the EDFA could be reduced, the OSNR of the transmitted signal can be increased and the fluctuation of the EDFA gain can be restrained in a certain scope by the CFBG employed in the system. Experiment of error-free 8×10 Gb/s 2015 km transmission without FEC and electric regeneration is demonstrated in this paper. In this system, only EDFA is used as amplifier,and no other form of dispersion compensator is adopted except CFBG. The experimental result showed that after 2 015 km transmission,the consistency of the dispersion compensating for each channel is perfect.