New operation mode for stacked-gate flash memory cell

A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells     

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.     

Optimization of word-line booster circuits for low-voltage flashmemories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed     

Offset word-line architecture for scaling DRAMs to the gigabitlevel

An alternative to the boosted word-line DRAM architecture is described that is scalable to the gigabit level and avoids the problems of poor performance and high gate fields of conventional boosted word-line circuits. The alternative is called an offset word-line architecture, because the cell switch is changed to depletion mode and the word line is pulled beyond the cell switch device's source voltage rather than boosted beyond its drain voltage. The large voltage swing for the word line does not cause large fields across the gate dielectric in the word-line driver or array access device because the gates of some devices use materials with modified work functions. The word-line voltage swing can be greater than the bit-line voltage swing plus the required threshold voltage even for gigabit-scale integration DRAM technologies     

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

A 32 Mb NAND type flash EEPROM has been developed with 0.425 μm CMOS technology. A 35 ns cycle time is achieved by adopting a pipeline scheme. A boosted word-line scheme and a program verify operation achieving tight threshold voltage (Vth) distribution of programmed cells reduce read-out access time. Multiple block erase operation is realized by adopting erase block registers. All functions are operable with a single 5.3 V or 5 V power supply     

A 256-Mb multilevel flash memory with 2-MB/s program rate for massstorage applications

A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm² die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V_th. The effect of adjacent memory cell's V_th is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V_th. In the -5-75°C range, memory threshold V_th deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector     

Novel self-limiting high-speed program scheme of p-channel DINORflash memory with n-channel select transistors

This paper describes a novel self-limiting high-speed program scheme of the p-channel DINOR (D_I_vided bit line N_O_R_) flash memory utilizing n-channel select transistors. This scheme makes it possible to maintain the high programming throughput of the p-channel DINOR even for future lower-voltage operation. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the only structural change from the conventional p-channel DINOR is the change of the impurity type of the select transistors, and the only operational change is the addition of a very short negative voltage pulse of 0.1 μs to each programming gate pulse. This shortness of the additional pulse hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for the realization of future, high-performance, lower-supply-voltage p-channel DINOR flash memories     

A double-level-Vth select gate array architecture formultilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-V_th select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized     

A new erasing and row decoding scheme for low supply voltageoperation 16-Mb/64-Mb flash memories

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories     

Contrasting single-wafer and batch processing for memory devices

Single-wafer technology has been shown to improve memory device performance and ultimately improve product yield for several front-end-of-line (FEOL) processes. Single-wafer processes that are reviewed include silicon nitride for word-line cap, flash oxide-nitride-oxide dielectric, cell dielectric re-oxidation, and selective oxidation.     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

Improvement of soft-error rate in MOS SRAMs

Two techniques which reduce the α-particle-induced soft-error rate (SER) in MOS static RAMs (SRAMs) are described. The mechanism of the soft error is the high-resistive load memory cell is analyzed. It is found that the dependence of SER on the cycle time is caused by the potential drop in the high storage node, which is produced by the threshold current through the driver and access transistors in the memory cell. Improvement methods to suppress the subthreshold current are presented. One method utilizes high-threshold-voltage transistors in the memory cell. The other sets the selected word-line level lower than the supply voltage. Using these methods, the high storage node potential is kept at the supply voltage in spite of the small conductance of the load resistor. The effect is confirmed in 256 kbit CMOS SRAMs. The dependence of SER on the cycle time becomes negligible, and SER is improved by two orders of magnitude     

多能级闪存的总剂量辐射效应

介绍了一种新型的存储技术——多能级存储,并对应用此技术的多能级闪存进行γ射线辐射,研究了多能级闪存的阈值电压及存储单元的电性能曲线等随辐射剂量、辐射剂量率以及时间的关系规律.对实验结果进行了理论解释和讨论     

Design concept for radiation hardening of low power and low voltagedynamic memories

A radiation hard low power, low voltage dynamic memory is obtained by the use of a dummy cell concept. Compared to conventional dummy cell concepts, this concept applies a fully sized dummy cell. By optimizing the dummy cell precharge voltage for 5 V and 3 V operation and the timing of the dummy word-line, the overall soft error rate (SER) of the chip is improved by 2 orders of magnitude. An additional improvement of 1 order of magnitude is possible for 3 V operation by adjusting substrate bias and cell plate voltage. The results are verified by an accelerated SER measurement with a radium 226 source and an additional field soft error study     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

Statistical simulations for flash memory reliability analysis and prediction

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements.     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput