多能级闪存的总剂量辐射效应

介绍了一种新型的存储技术--多能级存储,并对应用此技术的多能级闪存进行γ射线辐射,研究了多能级闪存的阈值电压及存储单元的电性能曲线等随辐射剂量、辐射剂量率以及时间的关系规律.对实验结果进行了理论解释和讨论.     

温度对辐射寿命影响的研究

本文通过计算,给出了温度对非常靠近的多上能级系统的辐射寿命的影响的一个公式,并与实验结果进行比较,二者符合甚好。     

气动CO2激光器中波长10.6微米和18.4微米同时准稳态振荡

红外激光辐射的共振作用是振动能级选择激发和多原子分子各振动型之间能量转移的有效手段此时，与泵浦能级的共振吸收一样,由于反转媒质吸收辐射，人们就可以利用有激发能级的分子感应“下落”到较低分布能级这一过程，在此过程中产生辐射增益或振荡。在辐射分子相互作用时间大大超过V-V转移的特性时间而小于V-T弛豫时间的非谐振荡系统中，“加热”振动模可能导致在单个V-T能级之间形成反射的准平衡分布。     

铯蒸气中的合作受激发射现象

在铯蒸气中,已得到7P和7S态之间的受激辐射。在磁场中,这些能级发生分裂。这时7P和7S之间的超精细跃迁仍保持受激辐射性质。我们认真观察了这个辐射带。当在某些磁场强度时,正好两对能级的频率相等。这时,两对能级的合作贡献达到振荡阈值,产生受激辐射。     

NAND闪存错误缓解技术综述

NAND闪存以其高存储密度、高速、低功耗等优点被广泛应用于数据存储。三维堆叠闪存技术的出现和多值存储技术的发展进一步提高了密度,降低了存储成本,同时也带来了更加严重的可靠性问题。闪存主控厂商一直采用更强大的纠错码(ECC),如BCH和LDPC码来对闪存中的数据错误进行纠正。但当NAND闪存中的错误数超出ECC纠错能力时,错误将无法被纠正,因此研究人员提出了多种基于NAND闪存的错误缓解技术作为ECC的补充方案。本文介绍了NAND闪存的工作原理和错误模式,对最新的错误缓解技术进行综述,为设计更加可靠的存储解决方案提供了有益参考。     

ThLXXXI、ULXXXIII离子2P~53l组态能级及2P~53l-3l’跃迁波长和振子强度计算

我们使用相对论多组态Dirac-Fock程序计算了ThLXXXI和ULXXXIII离子的2p~53l组态精细结构能级,以及2p~53l-3l′态跃迁波长和振子强度.计算结果表明,ThLXXXI、ULXXXIII离子在激光等离子体中能够产生波长λ<0.3mn软X射线相干辐射.这是天然最重的稳定元素类氖离子2p~53l组态能级跃迁所能产生的最短相干辐射波长值.     

类锂硅离子的辐射跃迁几率

在多组态Dirac-Fock(MCDF)理论框架下,精细地计算了类锂硅离子各能级(nl)_k-(nl)_k间(n_i≤5,n_k《12)的电偶极辐射跃迁几率,并据此得到了n《6各能级的辐射衰变速率;发现了高荷电类锂离子辐射跃迁的新规律。     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

类锂铝离子“纯原子”弛豫及粒子数布居的数值计算

本文运用碰撞—辐射模型,在给定的等离子体参数条件下,计算了“纯原子”弛豫过程及各能级的粒子数布居,并对计算结果进行了讨论。模型所需的能级结构、跃迁波长、振子强度及跃迁几率等原子参数,用Hartree-Fock自洽场方法计算得到。     

调QHo∶YAG激光器产生50mJ脉冲

操作在2mm光谱区的人眼安全脉冲激光在测距、遥感和激光雷达应用中非常有用。而且如果它们具有高峰值功率,那么在光学参量振荡器中有效输出转换在3～5mm与8～12mm区,这对许多遥感应用非常重要。北美纳什维尔BEA系统公司的科学家研制出共振抽运Ho∶YAG激光器,在14ns的调Q脉冲的2.09mm处产生的脉冲能量大于50mJ。激光器是“准二能级系统”,它能被光直接抽运到簇结构的上激光能级5I7,下能级非常靠近基态能级。因此仅有两个能级:上能级和“准”单态能级(包括低能级和基态能级)。低能级靠近基态能级引起显著的热布居,确保抽运辐射和激光辐射…     

An experimental confirmation of automatic threshold voltageconvergence in a flash memory using alternating word-line voltage pulses

A flash memory using the alternating word-line voltage pulses is experimentally studied. Relations between pulse count and the threshold voltages of the cell are obtained. An automatic threshold voltage convergence was confirmed by the relation, and the threshold voltage is successfully controlled by the word-line pulse voltage. An application to a multi-level flash memory is proposed     

闪速存储器的单管多位技术

为了在现有务件下进一步降低闪速存储器的单位成本，已开发了各种单管多位技术。文章着重介绍了基于浮栅结构的MLC技术和基于SONOS的单管多位技术。     

New operation mode for stacked-gate flash memory cell

A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells     

闪速存储器的研究与进展

介绍了闪速存储器的发展历史,分析了闪速存储器单元及电路的工作原理,并就“与非”结构闪速存储器进行探讨,最后讨论了在闪速存储器中应用的误差矫正码／电路和深亚微米（０．２５μｍ）闪速存储器技术。     

Energy-Aware Flash Memory Management in Virtual Memory System

The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for many portable devices with the continuing improvements on its capacity, reliability and much lower power consumption than mechanical hard drives. The characteristics of flash memory are quite different from a magnetic disk. Therefore, in this paper, we revisit virtual memory system design considering limitations imposed by flash memory. In particular, we focus on the energy efficient aspect since power is the first-order design consideration for embedded systems. Due to the write-once feature of flash memory, frequent writes incur frequent garbage collection thereby introducing significant energy overhead. Therefore, in this paper, we propose three methods to reduce writes to flash memory. The HotCache scheme adds an SRAM cache to buffer frequent writes. The subpaging technique partitions a page into subunits, and only dirty subpages are written to flash memory. The duplication-aware garbage collection method exploits data redundancy between the main memory and flash memory to reduce writes incurred by garbage collection. We also identify one type of data locality that is inherent in accesses to flash memory in the virtual memory system, intrapage locality. Intrapage locality needs to be carefully maintained for data allocation in flash memory. Destroying intrapage locality causes noticeable increases in energy consumption. Experimental results show that the average energy reduction of combined subpaging, HotCache, and duplication-aware garbage collection techniques is 42.2%.     

嵌入式系统下的64位Flash驱动程序设计

电子设备中经常使用Flash存储器存储数据,这必须配备相应的驱动程序.常用的Flash存储器芯片都有现成的驱动程序,但这些驱动程序都是针对单片Flash存储器的,而在实际系统中为满足存储空间的需求,通常将多片Flash存储器拼起来,为方便上层程序读写数据,驱动程序中必须考虑地址对齐问题.基于VxWorks操作系统,采用MPC8240 CPU,提出了4×16位Flash存储器驱动程序设计方法,讨论了各种情况下的地址对齐问题,给出了程序流程和部分源代码,并为上层程序提供了两个接口函数.     

大容量Flash与DSP接口技术的实现

简要介绍了ATMEL公司的32Mbit并行Flash存储器AT49BV322T的特点,以及TI公司的DSP TMS320F2407A的主要性能特点。详细介绍了AT49BV322T的几种工作模式和操作方式,存储器与DSP的硬件接口技术,实现了DSP对多片超大容量并行存储器寻址的连续性。同时介绍了DSP对存储器在线编程的软件,包括对存储器的配置、读操作、写入操作以及片擦除操作等。     

A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-Vpower supply

A 512-Mb flash memory, which is applicable to removable flash media of portable equipment such as audio players, has been developed. The chip is fabricated with a 0.18-μm CMOS process on a 126.6-mm² die, and uses a multilevel technique (2 bit/1 cell). The memory cell is AND-type, which is suitable for multilevel operation. This paper reports new techniques adopted in the 512-Mb flash memory. First, techniques for low voltage operation are described. The charge pump, control of pumps, and the reference voltage generator are improved to generate internal voltage stably for multilevel flash memory. Next, a method for reducing total memory cost in the removable flash media is described. A new operation mode named read-modify-write is introduced on the chip. This feature makes the memory system simple, because the controller does not have to track sector-erase information     

多密级交互存储控制器设计与实现

针对多密级信息环境下的数据交互问题,该文设计实现一种多密级交互存储控制器。在交互模型设计的基础上,构建了控制器总体结构,对存储器系统和交互控制逻辑等关键模块进行了详细设计,并实现了一个依据用户策略完成多密级信息交互的原型系统。实验结果表明,该文设计的多密级交互存储控制器,交互过程可由用户根据实际需求配置,能够实现多密级信息交互功能,对信息分级管理具有重要意义。     

Flash Memory测试技术发展

从Flash memory 测试技术的发展背景出发,论述了flash memory测试技术的发展现状以及前景.同时重点对Flash-march算法和BF&D算法进行了分析和评价.指出Flash memory的发展是以测试技术的发展为基础的,必须把Flash memory本身的发展和测试技术的发展综合考虑,才能有助于两者的协调发展.