JTIDS系统的低复杂度多进制扩频检测方法

传统多进制扩频调制使用多个相关器进行检测,每个相关器产生一个相关值,实现复杂.提出了一种使用FIR滤波器的基于扩频码段分路和延时相加的实用多进制扩频检测方法,通过FIR滤波即可产生所有相关值,实现结构简单,特别适合在使用周期移位伪随机序列的联合战术信息分发系统(JTIDS)中应用,可有效降低JTIDS系统中多进制扩频信号的检测复杂度和工程实现难度.仿真比较了优选扩频序列和Walsh正交码集的误比特率性能,获得了良好的性能结果.     

高速单片数字相关器VLSI结构研究

提出了一种高速单片数字相关器VLSI结构设计方法,结合扩频解扩芯片的实际需要,设计了包含16路数字相关器、集成规模达20万门的试验芯片,采用0.5μm三层金融CMOS工艺制造,测试表明,在3.3V工作电压和60MHz工作频率下,芯片的各项性能均达到设计要求。     

数字相关器在MSK扩频通信中的应用

讨论并分析了采用数字相关器的MSK扩频系统发射和接收基本原理。在PN码元的捕获系统中使用了一种改进的附加数字相关器。分析及实验结果表明,对于MSK扩频系统,低信噪比情况下能够正确解码,处理信号的形式灵活,免除了—般扩频系统中最难解决的PN码同步,并为位同步的提取带来了极大的方便;与数字相关器相比,能够简化捕获运算,且有效改善干扰。     

多载波直接序列扩频码分多址系统的性能分析

本文将多载波发送信号技术应用于直接序列扩频码分多址系统中。发射机中直接扩频序列与数据序列相乘,然后调制多个载波;接收机对每个载波进行相关,相关器的输出用最大比值合并。这种发送信号具有很好的窄带干扰压缩性能。文中估计了存在部份带宽干扰下系统的性能,并与单载波直扩码分多址系统进行了比较。     

多载波直接序列扩频码分多址系统的性能分析

本文将多载波发送信号技术应用于直接序列扩频码分多址系统中,发射机中直接扩频序列与数据序列相乘,然后调制多个载波;接收机对每个载波进行相关,相关器的输出用最大比值合并。     

一种适合于非相干直扩信号捕获的方法

介绍了非相干直接序列扩频的基本概念,并建立了非相干直接序列扩频信号基带传输模型;在此基础上研究了直接序列扩频中捕获的难点,并提出一种基于后相关滤波和功率检测的捕获方法;最后,根据工程需要对系统进行了简化。仿真结果表明提出的捕获方法是适合非相干直接序列扩频的,且性能接近相干直接序列扩频。     

码分射频识别的多进制扩展频谱编码传输研究

文章先简单介绍了m序列和移位m序列族有关特性,特别关注的是移位m序列族的序列间互衍生特性,这是移位m序列族多进制编码相关器获得简化设计的基础,再依据无源标签接收处于归一化信噪比极高的条件,提出移位m序列族多进制编码chip室相关器的设计方案.     

CDMA通信编码研究

扩频序列设计和选择是码分多址(CDMA)数字蜂窝移动通信的关键技术之一。扩频码序列的设计就是构造不同结构的具有良好特性的伪随机序列来满足CDMA系统的要求。目前研究最深入的和使用最多的是m序列和Gold序列及Walsh序列。文中从理论上和工程实用角度对扩频序列(m序列、Gold序列及Walsh序列等)的性能和特点进行了分析,同时给出了m序列、Gold序列及Walsh序列等的形成方法。     

GPS L1信号C/A码的高效并行软件相关器研究

在GPS软件接收机的捕获和跟踪算法中,相关器的运算是很大的计算负担,为了能够快速的计算,提出了一套用于GPS软件接收机的,处理CDMA扩频信号的软件相关器高效并行算法,主要针对耗时较多相关器进行算法优化,并给出了实际运行结果和性能分析,表明了本文提出的优化算法与直接浮点计算的方法相比,将软件相关器的处理速度提高了约4倍。而且,运用高效并行软件相关器的跟踪算法能够正确跟踪,并解调信号。介绍的相关器的设计方法适用于所有卫星导航系统的软件接收机。     

CDMA通信中多址序列相关性的研究及仿真

扩频序列设计和选择是码分多址(CDMA) 扩频通信的关键技术之一,扩频码序列的设计就是构造不同结构的具有良好相关性的伪随机序列来满足CDMA 系统的要求.现主要研究了应用于CDMA通信中的m序列、Gold序列和Kasami序列的原理、性能和构造方法,且基于MATLAB软件M语言编程以上序列的实现和相关性分析,并比较了其各自特点分析了其在不同环境下的适用性.     

PCB报价快速成本分析

文章着眼于对市场信息的快速反应,力求通过研究快速的PCB工程资牵片交计方法达到快速提供报价成本分析的目的.通过对工程资料设计规则和成本计算规则的分析研究,将两者有机结合起来.根据成本计算规则分析简化工程资料设计,通过分析工程资争日交计规则,建立优化程序,有针对性地简化工程资料设计.从而实现由快速的工程资料设计建立成本构成,再由成本构成快速产生成本分析报告.文章的创新点在于,基于成本计算规则研究建立快速的工程资料设计方法并开发相应的应用系统,从而快速实现成本明细分析,满足对市场信息的快速反应需求.     

A novel multiple-valued logic gate using resonant tunneling devices

We demonstrate a novel multiple-valued logic (MVL) gate using series-connected resonant tunneling devices. Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. We obtain the literal function, one of fundamental MVL functions, by integrating three InGaAs-based resonant-tunneling diodes with two HEMT's on an InP substrate. The gate configuration is greatly simplified compared with a conventional literal gate employing CMOS circuits     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

基于局部相关函数插值的二进制偏移载波调制信号码相位估计与鉴相方法

为了进一步提高卫星导航接收机对BOC(1,1)及其衍生类型调制信号的码鉴相的质量和跟踪能力,尤其是在高动态下的跟踪性能。该文提出一种基于局部相关函数插值的方法确定BOC(1,1)调制信号的码相位。该方法基于相关器阵列的结构,根据相关器阵列的输出值判断相关峰值的大致范围。利用广义延拓逼近的方法估计码相位的位置,同时在缺少延拓空间的情况下构造一个虚拟的相关器以完成对码相位的估计。该文具体分析了单侧相关器个数对牵入范围的影响,在此基础上对所提方法进行了计算机仿真实验。理论和仿真证明:所提方法能够在不增加过多硬件资源的条件下扩大码鉴相函数的线性牵入范围,进而能够提高接收机对于BOC调制信号的跟踪精度。     

通过腔QED实现高效的两原子的受控位相门

量子计算是近年来新出现的计算技术,具有非常好的发展前景.任何量子计算都能够被简化到一个门序列,而量子计算要利用某种物理体系来实现.介绍了一种通过腔QED实现高效的两原子的受控位相门的方案.此方案中,原子跃迁与腔模处于大失谐,因此原子自发辐射的影响得到了极大的抑制,从而提高了成功几率.而保真度取决于α、β、γ、δ几个常数的取值,数值计算结果表明我们的方案具有比较高的保真度,其保真度的平均值F=0.982318.该方案有一定的实验可行性,有望得到实验上的验证.     

Graphical design and iterative analysis of the DC parameters of GaAs FET's

Two-dimensional numerical solutions of Poisson's equation and the carrier continuity equation for the short-gate GaAS field-effect transistor structure have been used to predict device performance. However, a generally accepted simplified approach to FET design has not evolved. In this paper, a simplified design technique and an iterative device analysis procedure are presented for application to GaAs FET's with gate lengths as small as 1 µm. The design technique makes it possible to determine drain saturation current and saturation transconductance for any gate size by simply scaling the appropriate curves for an FET with a 1-µm gate. Curves are also presented that relate the effective transconductance to the intrinsic transconductance for any FET geometry. The iterative analysis procedure makes it possible to determine the doping, ND, and thickness, a, of the epitaxial layer on which the device is fabricated. By simply measuring drain current and transconductance at zero gate bias and the pinchoff voltage, a method is presented which allows the epi parameters to be determined in a self-consistent fashion. This technique provides a way of mapping NDand a over a slice, as opposed to the usual technique of simply measuring pinchoff voltage (only gives ND.a²product variations).     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Multiplexing Techniques for Digital Correlator Speed Improvement

Several approaches to time-division multiplexing of digital correlator devices are developed wherebykoperations are overlapped in time. Where synchronization with the input signal exists, the resulting multiplexed correlators providek-fold speed improvement over individual correlator devices. A completely synchronized correlator can be formed fromksuch multiplexed correlators by proper selection of outputs. A simplified realization is presented which only requires one set ofk N/k-bit signal and reference registers andksets ofN-bit comparator circuits. Laboratory experimentation and computer simulations to support these concepts are described.     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

A new simplified space-vector PWM method for three-level inverters

In this paper, a new simplified space-vector pulse width modulation (SVPWM) method for a three-level inverter is proposed. This method is based on the simplification of the space-vector diagram of a three-level inverter into that of a two-level inverter. If simplified by the proposed method, all the remaining procedures necessary for the three-level SVPWM are done like conventional two-level inverter and the execution time is greatly reduced. The DC-link neutral-point potential control algorithms are implemented more easily. The proposed method can be applied to the multi-level inverters above three-level. The validity of the new SVPWM method is verified by experiment with a 1000 kVA three-level insulated gate bipolar transistor (IGBT) inverter