Compact LDD nMOSFET degradation model

In this paper, we present a compact degraded I-V model for submicron lightly-doped drain (LDD) MOSFET's. The analytical and physics-based model was developed using the drift equation and considering the nonuniform spatial hot-carrier-induced interface states and the detailed LDD structure. It can be used to calculate fresh channel electric field and drain current by turning off the effect of hot-carrier-induced interface states. Using the fresh electric field in conjunction with a simplified energy balance equation, the nonuniform spatial distribution of induced interface states ran be calculated. By incorporating this distribution into the degraded current model, we can describe the damaged I-V characteristics and channel electric fields as a function of stress time. The model includes the effects of series resistances and carrier velocity saturation. It can be used to calculate time-dependent degraded drain current, and is a time-saving CAD model     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

A closed-form trapped-charge-included drain current compact model for amorphous oxide semiconductor thin-film transistors

A closed-form drain current compact model for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), including the influence from trapped charges, is presented in this paper. Accounting for both channel and interface trapped charges in this model, we explicitly solve the inherent closed-form surface potential by improving the computational efficiency of the effective charge density approach. Furthermore, based on the explicit solution of the surface potential, the expressions of the trapped and inversion charges in the channel film are derived analytically, and the drain current is integrated from the charge sheet model. Then, for the cases of the different operational voltages, the accuracy and practicability of our model are verified by numerical results of the surface potential and experimental data of the drain current in amorphous In-Ga-Zn-O TFTs, respectively. Finally, we give a discussion about the influence of the interface trapped charges on the device reliability. As a result, the model can be easily to explore the drain current behavior of the AOS TFTs for next-generation display circuit application.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs

The impact of hot-carrier degradation on drain current (I_D) hysteresis and switch-off I_D transients of thin gate oxide floating body PD SOI nMOSFETs is analyzed. An extended characterization of these floating body effects (FBEs) is carried out for a wide range of transistor geometries and bias conditions. The results show a link between the hot-carrier-induced damage of the front channel and the reduction of the FBEs. This is further supported by unbiased thermal annealing experiments, which are found to give rise to a partial recovery of the hot-carrier induced damage and FBEs.     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

Analytical modelling of electrical characteristics in γ-irradiated power VDMOS transistors

This paper deals with an analysis of γ-irradiation effects on basic electrical characteristics of power VDMOS transistors operated in both linear and saturation regions. First, an analytical model that yields the drain current and transconductance dependencies on gate oxide charge density is developed. The experimental data are utilized to establish a direct relation between the absorbed irradiation dose and the corresponding effective density of gate oxide charges. The drain current and transconductance of VDMOS devices are then modelled as the functions of radiation dose. Finally, the results of modelling are compared with experimental data.     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

Elementary ambipolar field-effect transistor model

An ambipolar FET can be operated alternatively in n-channel and p-channel modes. A simple conceptual model is proposed. It considers ohmic source and drain contacts, a gradual channel, and the depletion approximation.     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

4H-SiC埋沟MOSFET的研制

研制了4H-SiC热氧化生长氧化层埋沟nMOSFET.用室温下N离子注入的方法形成埋沟区和源漏区,然后在1600℃进行激活退火.离子注入所得到的埋沟区深度大约为0.2μm.从转移特性提取出来的峰值场效应迁移率约为18.1cm2/(V·s).造成低场效应迁移率的主要因素可能是粗糙的器件表面(器件表面布满密密麻麻的小坑).3μm和5μm器件的阈值电压分别为1.73V和1.72V.3μm器件饱和跨导约为102μS( V G=20V, V D=10V).