共查询到19条相似文献,搜索用时 234 毫秒
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利用自己开发的二维数值深亚微米SOI器件模拟软件,较为详细地分析了沟道长度小于o.2μm的 SOI器件的阈值电压特性、穿通和击穿特性、亚阈值特性以及直流稳态特性等.通过这些模拟和分析计算,给出了沟道长度为0.18、0.15和0.1μm的薄膜全耗尽 SOI/MOS器件的设计方案,并根据该设计方案成功地研制出了性能良好的沟道长度为0.15μm的凹陷沟道 SOI器件.沟道长度为0.15μm薄膜全耗尽凹陷沟道SOI器件的亚阈值斜率为87mV/dec,击穿电压为1.6V,阈值电压为0.42V,电源电压为1.5V时的驱动电流为1.85mA,泄漏电流为0.5pA/μm沟道宽度. 相似文献
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本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间. 相似文献
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本文提出适用于短沟道薄膜全耗尽SOI器件的大信号电容模型。该模型除考虑了SOI短沟道器件中出现的速度饱和效应、DIBL效应及源漏耗尽层电荷分享效应外,还包括了SOI器件中特有的膜厚效应、正背栅耦合效应等对电容特性的影响。通过与体硅器件的二维模拟和实测电容特性以及已报道的薄膜SOI器件电容模型相比较可知,本文模型可较好地描述短沟道SOI器件的电容特性。另外,所建电容模型形式简洁,参数提取方便,因而可做为薄膜全耗尽SOI器件大信号电容模型移植到电路模拟程序(如SPICE)之中。 相似文献
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本文提出适用于短沟道薄膜全耗尽SOI器件的大信号电容模型。该模型除考虑了SOI短沟道器件中出现的速度饱和效应、DIBL效应及源漏耗尽层电荷分享效应外,还包括了SOI器件中特有的膜厚效应、正背栅耦合效应等对电容特性的影响。通过与体硅器件的二维模拟和实测电容特性以及已报道的薄膜SOI器件电容模型相比较可知,本文模型可较好地描述短沟道SOI器件的电容特性。另外,所建电容模型形式简洁,参数提取方便,因而可做为薄膜全耗尽SOI器件大信号电容模型移植到电路模拟程序(如SPICE)之中。 相似文献
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A junction breakdown model and the results of PISCES II simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in fully depleted (FD) SOI diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SOI diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measurements of separation by implantation of oxygen (SIMOX)-based SOI diodes, the results of which suggest that body breakdown is dominant in FD SOI diodes, and the junction curvature effect is dominant in PD SOI diodes. Furthermore, the results also show that breakdown voltage in the FD SOI diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias 相似文献
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Kilchytska V. Neve A. Vancaillie L. Levacq D. Adriaensen S. van Meer H. De Meyer K. Raynaud C. Dehan M. Raskin J.-P. Flandre D. 《Electron Devices, IEEE Transactions on》2003,50(3):577-588
This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS). 相似文献
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Jae-Ki Lee Nag-Jong Choi Yun-Bong Hyun Chong-Gun Yu Jean-Pierre Colinge Jong-Tae Park 《Electron Device Letters, IEEE》2002,23(3):157-159
The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested 相似文献
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Ying-Che Tseng Huang W.M. Diaz D.C. Ford J.M. Woo J.C.S. 《Electron Device Letters, IEEE》1998,19(9):351-353
We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications 相似文献
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This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT. 相似文献
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研究了射线辐照对130 nm部分耗尽(Partially Depleted,PD)绝缘体上硅(Silicon on Insulator,SOI)工艺MOS器件栅氧经时击穿(Time-Dependent Dielectric Breakdown,TDDB)寿命的影响。通过测试和对比辐照前后NMOS和PMOS器件的转移特性曲线、阈值电压、关态泄漏电流以及TDDB时间等电参数,分析了射线辐照对PD-SOI MOS器件TDDB可靠性的影响。结果表明:由于射线辐照在栅极氧化层中产生了带正电的氧化物陷阱电荷,影响了器件内部势垒的分布,降低了电子跃迁的势垒高度,导致了电子遂穿的正反馈作用增强,从而缩短了器件栅氧化层经时击穿时间,最终造成器件栅极氧化层的可靠性下降。 相似文献
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Ying-Che Tseng Huang W.M. Mendicino M. Monk D.J. Welch P.J. Woo J.C.S. 《Electron Devices, IEEE Transactions on》2001,48(7):1428-1437
Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology 相似文献
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Jae-Ki Lee Nag-Jong Choi Chong-Gun Yu Colinge J.-P. Jong-Tae Park 《Electron Device Letters, IEEE》2002,23(11):673-675
The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant. 相似文献
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Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET 总被引:8,自引:0,他引:8
The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration. 相似文献