用遗传算法实现CMOS时序电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的。实际中,总是在有限的计算时间内获取一个近似最大功耗。文中用遗传算法来选择具有高功耗的输入及内部状态模型,对电路进行仿真,实现时序电路的最大功耗估算;同时,实现了基于统计的逻辑模拟最大功耗估计方法。基于ISCAS89基准时序电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高。而且新方法的计算时间基本上是电路逻辑门的线性关系。     

VSF:CMOS组合电路的静态功耗评估模型

为了解决利用晶体管级电路模拟分析CMOS电路静态功耗时模拟时间随电路规模增大迅速增加的问题,在分析晶体管堆叠效应对标准单元泄漏电流影响的基础上,定义了归一化堆叠系数和电路等效堆叠系数的概念,提出了基于电路有效堆叠系数的静态功耗评估模型.该模型可用于CMOS组合电路静态功耗估算和优化.实验结果表明使用该模型进行静态功耗估算时,不需要进行Hspice模拟.针对ISCAS85基准电路的静态功耗优化结果表明,利用该模型能够取得令人满意的静态功耗优化效果,优化速度大大提高.     

VSF:CMOS组合电路的静态功耗评估模型

为了解决利用晶体管级电路模拟分析CMOS电路静态功耗时模拟时间随电路规模增大迅速增加的问题,在分析晶体管堆叠效应对标准单元泄漏电流影响的基础上,定义了归一化堆叠系数和电路等效堆叠系数的概念,提出了基于电路有效堆叠系数的静态功耗评估模型.该模型可用于CMOS组合电路静态功耗估算和优化.实验结果表明使用该模型进行静态功耗估算时,不需要进行Hspice模拟.针对ISCAS85基准电路的静态功耗优化结果表明,利用该模型能够取得令人满意的静态功耗优化效果,优化速度大大提高.     

MOS电流模逻辑加法器结构设计

为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

一种基于多数决定门的新型全加器的设计

在对现有全加器电路研究分析的基础上,提出了一种基于低功耗XOR/XNOR电路和多数决定门的新型高性能全加器电路.多数决定门采用输入电容和静态CMOS反相器实现,降低了电路的功耗,提高了运算速度.采用TSMC 0.18 μm CMOS工艺器件参数,对全加器进行Spectre仿真.结果表明,在2.4 V到0.8 V电源电压范围内,与已有的全加器相比,新全加器在功耗和延迟上都有较大程度的改进.     

AND/XOR电路低功耗映射及其在最佳混合极性搜索中的应用

本文提出一种工艺无关的AND/XOR电路低功耗映射算法。该算法通过优化电路节点开关活动性实现静态MPRM电路平均功耗最小化,根据给定工艺库中的逻辑门估算MPRM电路的功耗和面积。在此基础上,结合极性转换算法获得任意极性的MPRM电路,利用遍历搜索法快速找到最佳混合极性。通过对18个MCNC和ISCAS基准电路测试表明：与FPRM电路和AND/OR电路功耗优化方案相比,混合极性搜索方案获得的AND/XOR电路功耗平均节省分别可达44.22%和60.09%,面积平均节省分别可达14.13%和32.72%。     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式——能量回收阈值逻辑电路(energyre-coverythresholdlogic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%     

150Ms/s、6bit CMOS数字工艺折叠、电流插值A/D转换器

在1.2μm SPDM标准数字CMOS工艺条件下,实现6bit CMOS折叠、电流插值A/D转换器;提出高速度再生型电流比较器的改进结构,使A/D转换器(ADC)总功耗下降近30%;提出一种逻辑简单易于扩展的解码电路,以多米诺(Domino)逻辑实现.整个ADC电路中只使用单一时钟.在5V电压条件下,仿真结果为采样频率150-Ms/s时功耗小于185mW,输入模拟信号和二进制输出码之间延迟小于2个时钟周期.     

冒险共振现象及其在CMOS电路最大功耗估计中的应用

随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。     

Maximum power estimation for CMOS circuits using deterministic andstatistical approaches

Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent input-pattern dependence of the problem, it is impractical to conduct an exhaustive search for circuits with a large number of primary inputs. Hence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of central processing unit (CPU) time. In this paper, instead of using the traditional simulation-based techniques, we propose a novel approach to obtain a lower bound of the maximum power consumption using automatic test generation (ATG) technique, Experiments with MCNC and ISCAS-85 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques. In addition, a Monte Carlo-based technique to estimate maximum power dissipation is described. It not only serves as a comparison version for our ATG approach, but also generates a metric to measure the quality of a lower bound from a statistical point of view     

基于GSAA算法的组合电路最大功耗估计方法

最大功耗估计问题是一个NP难题。提出的方法利用遗传模拟退火算法(GSAA)在整个解空间快速搜索问题的最优解，实现组合电路最大功耗的快速、精确估计。仿真结果表明，提出的方法比基于遗传算法(GA)的估计方法在估算精度和收敛速度上都有提高，适合于大规模组合电路最大功耗的估计。     

一种基于遗传算法的VDSM IC电源网格动态IR-drop分析新方法

提出了一种用于超深亚微米集成电路电源网格IR-drop验证的新方法.该方法以遗传算法为基础,与已有的分析方法相比,该方法兼具静态IR-drop分析法和动态IR-drop分析法的优点,适用于包含大型组合模块的超大规模集成电路,可主动寻找电路中最大IR-drop.通过对ISCAS85电路实现的验证,发现了静态分析法不能发现的芯片边缘IR-drop问题.实验结果验证了该方法的正确性与有效性.     

GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.     

Petri net modeling of gate and interconnect delays for power estimation

Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS '89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.     

Variation-aware approaches with power improvement in digital circuits

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.     

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon     

Efficient statistical approach to estimate power consideringuncertain properties of primary inputs

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately