基于电磁兼容的高速无线节点PCB设计与仿真

在无线节点PCB的设计过程中,由于存在高速电路,所以不可避免的会出现电磁兼容问题.对自动布线后的信号线进行仿真发现反射和串扰对信号的影响较大.根据电磁兼容布局布线原则对出现问题的信号线手动调整参数重新布线,调整后再一次进行仿真,此时反射和串扰得到了有效的抑制.由此可见,根据电磁兼容设计原则手动布线后的PCB性能优于自动生成的PCB布线设计.     

CEE-Gr:一个在多约束下进行性能优化的总体布线器

提出了一个在多约束下进行性能优化的总体布线算法.研究了在总体布线阶段同时进行RLC耦合噪声(串扰)、时延性能和布线拥挤优化的问题.根据所提出的算法思想已实现了相应的总体布线器:CEE-Gr.并对所实现的总体布线器CEE-Gr进行了MCNC电路例子的测试,得到令人满意的结果.     

使用防护布线减小差分传输线间的高频串扰噪声

随着高速电路的不断发展,差分传输线得到了越来越广泛的应用。它具有低辐射和较好的抗共模噪声能力。但是传统的差分线结构不能有效的降低邻近差分对之间的串扰噪声,这将影响到高速系统的信号完整性。文章针对使用防护布线的方法,讨论了三种不同结构的防护布线,在全波电磁仿真软件HFSS中建立了三维物理模型,利用混模S参数分析了它们对于减小串扰噪声的作用,从场的角度对比了它们的电磁屏蔽效果,并对如何使用防护布线提出了一些建议。     

考虑串扰效应的性能驱动全局布线器研究

提出了利用符号化矩计算模型进行性能驱动的多级布线方法.通过在模式布线阶段利用符号化矩计算模型,快速得到电路的高阶矩,并根据计算结果,采用合理的代价函数对时延串扰等性能指标进行预估,进而指导布线.实验结果显示,该算法在串扰优化方面得到较大的提高,布线结果兼顾了时延优化和信号波形质量优化.     

CEE-Gr:一个在多约束下进行性能优化的总体布线器

提出了一个在多约束下进行性能优化的总体布线算法 .研究了在总体布线阶段同时进行 RL C耦合噪声 (串扰 )、时延性能和布线拥挤优化的问题 .根据所提出的算法思想已实现了相应的总体布线器 :CEE- Gr.并对所实现的总体布线器 CEE- Gr进行了 MCNC电路例子的测试 ,得到令人满意的结果.     

CMOS混合信号集成电路中的串扰效应

论述了混合信号集成电路中的串扰效应及其对电路本身的影响,重点讨论了在重掺杂衬底中数字干扰对模拟器件的影响,并给出了数字噪声注入等效电路.同时从制造工艺和设计技术方面讨论了降低串扰效应的方法.     

高速电路中平行传输线间的串扰分析及解决方案

当今电子设计领域正快速朝着大规模、小体积、高速度方向发展,而体积减小导致电路的布局布线密度变大,同时信号的频率还在提高,使得串扰成为高速、高密度PCB设计中值得关注的问题。介绍了高速电路中串扰的产生机理,并用HyperLynx[3]对串扰进行数值仿真,通过分析提出减小串扰的一些实用方法。这对于在高速、高密度电路设计中解决串扰问题具有十分重要的意义。     

高速时钟电路的可靠性设计

本文介绍单片机及数字电路系统中高速时钟电路可靠性设计思路与方法,提出了高速时钟源的电源滤波电路的可靠性设计方法、提出了如何解决高速时钟走线的串扰问题手段、高速时钟延时调整及处理方法、高速时钟信号布线方法.     

动态串扰优化的开关盒布线

针对超深亚微米芯片设计中的开关盒布线问题提出了可变参数的串扰优化布线算法.该算法充分利用了双层布线资源,将动态信号波形和耦合电容结合起来考虑,进一步减小了线网间的总串扰,并力求通孔数最少.实验证明,本算法能够获得更加优化的布线方案.     

平行传输线间串扰的仿真及分析

在高速电路设计中,信号完整性问题越来越突出,已经成为高速电路设计师不可避免的问题。该文重点研究了平行传输线间的串扰问题,通过信号完整性分析软件Hyperlynx建立了三线串扰模型并进行仿真分析,最后提出高速PCB设计中减小串扰噪声的策略。     

高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题.利用高速电路仿真软件HSPICE和MATLAB软件,对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线问的串扰规律,对部分串扰规律进行了探索性的研究.     

Design limitations of highly parallel free-space opticalinterconnects based on arrays of vertical cavity surface-emitting laserdiodes, microlenses, and photodetectors

We utilize a novel diffraction formalism to study the crosstalk effect in a highly parallel free-space optical interconnect based on two-dimensional arrays of surface-emitting laser diodes, microlenses, and photodetectors. The diffraction induced crosstalk between adjacent laser diodes in each detector to the system limitations is investigated. Optimum design rules and formulas are given for the first time, to include the relation of channel packaging density and interconnect length to the design parameters of the optical interconnect components. The design formulas developed here yield an optimum detector size and indicate a tradeoff between channel packaging density and interconnect length. The feasibility of such a free-space interconnect with a channel packaging density of 3460 channels/cm² and 2.0 cm interconnection length is determined using typical parameters of detector radius from ~5 to ~45 μm, lens radius of 85 μm, and laser diode radius of ~5 pm operating at wavelength 0.67 pm for signal-to-noise ratio above 17 dB. Some experiments were conducted to measure the diffraction induced crosstalk and optical link efficiency     

Fast coupled noise estimation for crosstalk avoidance in the MCGmultichip module autorouter

A multilayer, multichip module (MCM) router, called MCG, is introduced for x-y routing. An efficient method has been derived to allow candidate routes for the nets to be considered simultaneously for compatibility rather than incrementally extending routes or routing one net at a time as in many other techniques. This allows incorporation of accurate models for determining the potential for crosstalk problems during the routing process. MCG incorporates a crosstalk avoidance procedure which facilitates correct-by-design routing in systems susceptible to noise problems. In comparisons with other routers on industrial benchmarks, the MCG router has shown substantial improvement in routing density, number of layers, number of vias, and total interconnect length over routers such as V4R and SLICE. Our test results show up to 18% improvement in via count and up to 33% improvement in the required number of routing layers for these examples over V4R. One of the benchmarks presented contains 37 VHSIC gate arrays, over 7000 nets, and over 14000 pins (pads). Routing at finer pitches with crosstalk avoidance shows a further improvement in interconnect density     

TMR voting in the presence of crosstalk faults at the voter inputs

In high reliability systems, the effectiveness of fault tolerant techniques, such as Triple-Modular-Redundancy (TMR), must be validated with respect to the faults that are likely in the current technology. In todays' Integrated Circuits (IC), this is the case of crosstalks, whose importance is growing because of device & interconnect scaling. This paper analyzes the problem of crosstalk faults at the inputs of voters in TMR systems. In particular, possible problems are illustrated, and it is shown that such crosstalk may invalidate the reliability of both voting, and diagnosing operations. The problem is analyzed from a probabilistic point of view. Its occurrence is estimated by using a set of TMR systems obtained with combinational benchmarks as functional modules. The possible problems of such operations are discussed in the presence of crosstalk faults. It is shown that crosstalk may invalidate the reliability of both voting, and diagnosis operations. A probabilistic model of the voting & diagnosis operations in the presence of crosstalk has been developed. Finally, such a model has been used to estimate the probability of voting & diagnosis failures in a set of TMR systems obtained by using combinational benchmarks as functional modules. We have shown that the presence of crosstalk faults at voter inputs may impair both the voting, and the diagnosis mechanisms. This problem has been quantified by applying a probabilistic model of crosstalk fault effects on voting and diagnosis to a set of benchmark circuits. Results show that crosstalk may create a reliability problem for TMR systems. Such a problem can be solved by using on-line testing or design for testability providing additional controllability & observability to the replicated functional units.     

Design and Characterization of the EBG Waveguide-Based Interconnects

An alternative signal guiding structure, which can be integrated within the printed circuit substrates, is investigated in this paper. The structure is realized by forming a rectangular waveguide in a 2-D electromagnetic bandgap (EBG) substrate. In this manner, a bandpass interconnect is provided that proves to be a promising technology for the high-speed/high-frequency system design. A systematic approach to the design and optimization of this interconnect is presented here followed by investigation of various bend geometries. The studied structures exhibit very low levels of loss and leakage when inspected at tens of gigahertz frequency range. Moreover, the near-end and the far-end crosstalks are monitored in multiple interconnects proving the high efficiency of this alternative routing structure in dense layouts. Nonetheless, the crosstalk performance is degraded as the coplanar microstrip-to-waveguide transitions are added. These transitions are essentially tapered microstrip lines that are connected to other circuitries. Continuous via fences are inserted in the transition sections of multiple structures demonstrating significant improvement in the crosstalk performance.     

两相邻耦合RC互连的串扰效应及其抑制

随着深亚微米设计的发展,互连线串扰变得更加严重.文中分析了深亚微米集成电路设计中对两相 邻耦合RC互连串扰的成因,论述了在设计中抑制串扰一般方法.     

一款深亚微米ASIC芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使芯片版图设计师需深入介入物理设计,选用有效的EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Cadence公司Soc Encounter后端工具对基于0.18μm工艺的ASIC芯片后端设计过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题,以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

百万门系统级芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使百万门级芯片版图设计师需深入物理设计,选用有效EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Synopsys公司Astro后端工具对一款百万门级、基于0.18μm工艺SoC芯片后端设计的过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

高密度封装中互连结构差分串扰建模与分析

针对传统模型存在较大分析误差的问题,提出高密度封装中互连结构差分串扰建模与分析。在对互连结构差分传输线耦合关系分析的基础上,建立了四线差分结构串扰模型。运用该模型对互连结构差分串扰中的电阻、电容以及电感进行等效分析,解决高密度封装中互连结构差分串扰问题。经试验证明,此次建立模型平均误差为0.042,满足抑制高密度封装中互连结构差分串扰问题的精度需求。     

On the design of multi-wavelength copy interconnects with reduced complexity

A multi-wavelength copy interconnect is a switching network capable of replicating a signal arriving at the input on a specific wavelength to one or more outputs possibly on different wavelengths. Such an interconnect can be useful in building optical multicast switches for wavelength division multiplexing (WDM) networks. In this article, we investigate, for the first time, the problem of designing copy networks that can simultaneously multicast input signals to a set of outputs while changing the wavelength of the replica according to the required routing pattern. We propose a novel multi-wavelength crossbar (MWX) switch that can switch an input signal on a specific wavelength to two different output wavelengths. The proposed MWX is used as a building block to construct two classes of multi-log_2N copy networks, namely, baseline and Bene? interconnects. The design space of the proposed interconnect classes is characterized and their hardware complexity is analyzed. We show that the proposed interconnects are transparent to existing multicast routing algorithms, and present simple routing algorithms for routing of multicast requests over the proposed designs. Comparisons with existing designs confirm that the proposed interconnects require a smaller number of space switches and wavelength conversion processes as compared to most conventional copy networks. In particular, for a large number of wavelengths and for any number of fibers the proposed design requires 50% less switching elements as compared to best available designs.