基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型

在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.     

竞争硬故障与软故障失效模式产品的可靠性分析

根据系统可靠性理论,考虑到硬故障和软故障两种竞争失效模式对产品失效的影响,对传统的可靠性分析方法进行了扩展。研究了满足硬故障和软故障竞争失效规则的产品可靠性函数和失效率函数。并通过不同的失效模式之间的关系。得到产品在不同的硬、软故障模式下的失效分布函数。另外还给出一个简单的算例来说明该分析方法的应用。该分析方法可能更符合机电产品的失效规律。     

基于离散模型的IC可靠性与成品率关系

集成电路的可靠性和成品率是制约半导体制造发展的两个主要因素.如何表征可靠性和成品率之间的关系是一个非常重要的问题.本文利用一种离散的成品率模型导出了二者的关系式,该关系式不仅考虑了线宽、线间距等版图的几何信息同时还考虑了与工艺有关的缺陷粒径分布等参数.通过模拟实验给出了该模型的有效性验证.     

硅片缺陷粒径分布参数的提取方法

利用电学测量方法,给出了在集成电路制造过程中,影响光刻工艺的各种颗粒尘埃(缺陷)的粒径分布参数提取方法.首先基于双桥微电子测试结构,通过具体制造工艺得到数据,然后处理得到故障的粒径分布.再利用缺陷与故障之间的关系,进一步推导出缺陷粒径分布的参数.结果表明该方法适合于不同的缺陷粒径分布模型,而且得到的参数可以用于集成电路成品率预测.     

硅片缺陷粒径分布参数的提取方法

利用电学测量方法,给出了在集成电路制造过程中,影响光刻工艺的各种颗粒尘埃(缺陷)的粒径分布参数提取方法.首先基于双桥微电子测试结构,通过具体制造工艺得到数据,然后处理得到故障的粒径分布.再利用缺陷与故障之间的关系,进一步推导出缺陷粒径分布的参数.结果表明该方法适合于不同的缺陷粒径分布模型,而且得到的参数可以用于集成电路成品率预测.     

一个面向缺陷分析的电路成品率与可靠性的关系模型

在电路设计的早期阶段,成品率与可靠性的关系模型对于预测和改善电路的成品率和可靠性具有极为重要的意义.结合广义门电路的版图结构与拓扑结构信息,分析了其缺陷密度及成品率和可靠性的损失机理,并构建了考虑缺陷生长特性的广义门电路成品率与可靠性损失概率之间的解析关系模型.基于该模型,又考虑到电路拓扑结构对故障的屏蔽效应,利用迭代的概率转移矩阵方法给出了门级电路成品率与可靠性之间的量化关系.理论分析与通过在ISCAS85基准电路上采用经验公式和惯用方法的证明策略,验证了本文所提方法的合理性和有效性.还分析了工艺参数、老化因素等对电路成品率与可靠性关系的影响.     

基于IC互连线开路故障的Y/R模型

在半导体制造业中,IC的成品率和可靠性(Y/R)是倍受关注的两个问题.研究表明它们之间存在着显著的相关性.为了表征这种相关性,本文从缺陷造成互连线开路的机理出发,分析了成品率关键面积和可靠性关键面积,提出了IC成品率与可靠性关系模型.通过模拟实验给出了该模型的有效性验证.     

微电子学、集成电路

TN4 2003010817硅片缺陷粒径分布参数的提取方法/郝跃,陆勇,赵天绪,马佩军(西安电子科技大学))I半导体学报一2 002,23(3)一315一318利用电学测量方法,给出了在集成电路制造过程中,影响光刻工艺的各种颗粒尘埃(缺陷)的粒径分布参数提取方法.首先基于双桥微电子测试结构,通过具体制造工艺得到数据,然后处理得到故障的粒径分布.再利用缺陷与故障之间的关系,进一步推导出缺陷粒径分布的参数.结果表明该方法适合于不同的缺陷粒径分布模型,而且得到的参数可以用于集成电路成品率预测.图5参11(木)数,从测量数据计算了集成电感的参量.实验的侧向螺…     

基于缺陷统计分布的IC互连线可靠性模型

讨论了电路在直流和脉冲直流工作情况下互连线的寿命,并重点考虑了工艺缺陷软故障的影响,提出了新的互连线寿命估计模型.利用该模型可以估算出在考虑缺陷的影响时互连线的寿命变化情况,这对IC电路设计有一定的指导作用.模拟实验证明了该模型的有效性.     

基于缺陷统计分布的IC互连线可靠性模型

讨论了电路在直流和脉冲直流工作情况下互连线的寿命 ,并重点考虑了工艺缺陷软故障的影响 ,提出了新的互连线寿命估计模型 .利用该模型可以估算出在考虑缺陷的影响时互连线的寿命变化情况 ,这对 IC电路设计有一定的指导作用 .模拟实验证明了该模型的有效性     

Equivalent circular defect model of real defect outlines in the ICmanufacturing process

For efficient yield prediction and inductive fault analysis of integrated circuits (IC's), it is usually assumed that defects related to photolithography have the shape of circular discs or squares. Real defects, however, exhibit a great variety of shapes. This paper presents an accurate model to characterize those real defects. The defect outline is used in this model to determine an equivalent circular defect such that the probability that the circular defect causes a fault is the same as the probability that the real defect causes a fault, so a norm is available which ran be used to determine the accuracy of a defect model, and thus estimate approximately the error that will be aroused in the prediction of fault probability of a pattern by using circular defect model. Finally, the new model is illustrated with the real defect outlines obtained by optical inspection     

一种有效的IC成品率估算模型

从缺陷造成电路故障的机理出发,给出了芯片故障概率和成品率的计算新模型.利用IC功能成品率仿真系统XD-YES对实际电路XT-1成品率参数的提取,同时利用新模型进行计算,其结果与实际结果符合很好.     

Quality and reliability impact of defect data analysis

In the last decade we have seen a shift towards a broader application of information on IC manufacturing defects. Here an overview is given of the methods used to gather data on the defects with a focus on local defects in the interconnection layers. Next this information is applied to determine a model describing the geometrical aspects of such defects. This model is used to arrive at a definition of hard faults and soft faults and to derive a relationship between the relative number of occurrence for either fault. Because the electrical impact of some of the soft faults will be closely related to the behavior of small open circuits or gate-oxide shorts, this relationship is an indication for the extent of the quality and reliability problems     

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.     

Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, due to the ease of testing and the good correlation to the yield characteristics of logic circuitry. For the identification of the failure/fault type and the nature of the defect causing the failure, measured failbitmaps are mapped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several faults or defects.In this contribution, the application of current signature analysis is demonstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved considerably by additional current signature measurements. The interpretation of current measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current test. There was good agreement between the simulated and measured current values.With the aid of current measurements, more yield learning information is obtained from the process monitoring vehicle. In some cases, the shorted nodes inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation in physical failure analysis.     

A separable method for incorporating imperfect fault-coverage intocombinatorial models

This paper presents a new method for incorporating imperfect FC (fault coverage) into a combinatorial model. Imperfect FC, the probability that a single malicious fault can thwart automatic recovery mechanisms, is important to accurate reliability assessment of fault-tolerant computer systems. Until recently, it was thought that the consideration of this probability necessitated a Markov model rather than the simpler (and usually faster) combinatorial model. SEA, the new approach, separates the modeling of FC failures into two terms that are multiplied to compute the system reliability. The first term, a simple product, represents the probability that no uncovered fault occurs. The second term comes from a combinatorial model which includes the covered faults that can lead to system failure. This second term can be computed from any common approach (e.g. fault tree, block diagram, digraph) which ignores the FC concept by slightly altering the component-failure probabilities. The result of this work is that reliability engineers can use their favorite software package (which ignores the FC concept) for computing reliability, and then adjust the input and output of that program slightly to produce a result which includes FC. This method applies to any system for which: the FC probabilities are constant and state-independent; the hazard rates are state-independent; and an FC failure leads to immediate system failure     

子网络级模拟故障诊断的神经网络实现

利用容差模拟电路节点电压灵敏度序列守恒定理,得到了模拟电路元件的软、硬故障统一样本。然后利用统一样本集训练BP神经网络,并将神经网络用于子网络级模拟故障诊断。实例验证表明,软、硬故障统一样本集使得用于神经网络训练所需样本数目大大减少,但经过训练的神经网络可以诊断容差模拟电路的全部软、硬故障,而且诊断正确率较高。     

全新的光突发交换网络数据信道性能与故障监测机制

在首次提出探测突发概念的基础上,提出了一种全新的光突发交换网络数据信道性能与故障监测机制,即网元节点向数据信道周期性地或以某种特定方式发送探测突发,并在每个下一跳节点监测探测突发的误码情况,分析其误码特点,依此来评估每两个节点间的数据信道状态,判断被监测网络是否有故障发生.该机制能在很短时间内定位突然中断或恶化的故障信道,还可对所监视网络的老化等软故障进行有效的预警和评估,具有很高的实用价值和可操作性.