共查询到19条相似文献,搜索用时 46 毫秒
1.
2.
SOI器件具有高速、低压、低功耗、抗辐照、耐高温等体硅器件不具备的优点,SOI CMOS技术开始用于深亚微米高速、低功耗、低电压大规模集成电路应用。但SOI技术还面临浮体效应、自加热效应等问题的挑战。作为SOI模型国际标准,BSIM3SOIv1.3提出了新的模型参数解决方案。BSIMPDSPICE器件模型是基于物理意义的模型,是在体硅MOS器件模型工业标准(BSIM3V3)的基础上开发而成,BSIMPD针对SOI固有的浮体效应引起的动态特性,自加热和体接触提出相应的模型参数。 相似文献
3.
4.
5.
6.
7.
8.
9.
10.
11.
Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating. 相似文献
12.
13.
The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction 相似文献
14.
Workman G.O. Fossum J.G. Krishnan S. Pelella M.M. Jr. 《Electron Devices, IEEE Transactions on》1998,45(1):125-133
To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature 相似文献
15.
Suma K. Tsuruda T. Hidaka H. Eimori T. Oashi T. Yamaguchi Y. Iwamatsu T. Hirose M. Morishita F. Arimoto K. Fujishima K. Inoue Y. Nishimura T. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》1994,29(11):1323-1329
An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc=3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80°C is longer than 20 s (Vcc=3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's 相似文献
16.
The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition. 相似文献
17.
This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device. 相似文献
18.
The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology. 相似文献
19.
Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and VDD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior 相似文献