电网系统中瞬间电压降对用电设备的危害分析

分析了电网系统中瞬间电压降的产生原因,并从用电设备的物理机制入手,重点分析了电网系统中瞬间电压降对系统内用电设备的危害,同时针对具体情况,给出了经济有效的解决办法。     

层状结构铁电薄膜中频率对界面电位降的影响

利用准分子激光原位沉积方法制备了层状结构铁电薄膜,借助HP4192A低频率阻抗分析仪对样品的C－V特性进行了测试,对同一频率下不同结构的铁电薄膜的界面电压降及不同频率下同一结构的铁电薄膜的界面电压降进行计算。结果表明,在同一频率下不同结构的铁电薄膜其界面电压降不同,同一结构的多层铁电薄膜在不同频度下其界面电压降也不同。不同的耗尽层厚度导致了界面电压降的不同。     

利用Astro-Rail分析FFT芯片的功耗和电源完整性

本文介绍如何使用Synopsys公司的Astro-Rail工具对采用SMIC0.18μmCMOS工艺、已完成布局布线的FFT芯片进行功耗分析、电压降分析和电迁移分析。通过在电压降图和电迁移图中用不同的颜色来显示不同区域的电压降和电迁移情况,可判断出最有可能出现问题的区域。文中利用功耗分析证明了电源和地PAD对的数目符合要求,利用电压降分析和电迁移图证明了电源环和电源条的布置符合工艺要求。     

利用降压转换器为便携设备供电

PDA及笔记本电脑等便携式产品若采用锂电池为其微处理器供电,在一般情况下都会采用小型而又具能源效益的降压直流-直流转换器。若以转换效率作为衡量标准,开关稳压器才是佳的选择。若元件高度受到限制,便不能使用电感(移动电话等便携设备常受此限制)。在这种情况下,采用低压降(LDO)线性稳压器作为转换器可能是一个较为理想的选择。只要微处理器电压接近电池电压,外型小巧且成本低廉的低压降芯片便可发挥其最高的效率。若电压差距太大,低压降芯片的效率便会大打折扣。     

利用VoltageStorm和APSI工具进行chip-package静态电源分析

目前的片上系统(SoC)设计特点是持续增大的芯片尺寸,集成更多的IP模块,多种电源电压供电,以及封装对供电电压的影响,这加大了不可预测的电压降带来芯片失败的风险。为降低此风险,可使用Cadence公司的SoC电源完整性分析和验证工具VoltageStorm,并结合APSI提取的封装模型,进行chip-package电源完整性分析。本文将结合实际设计项目,介绍利用Cadence公司VoltageStorm和APSI工具进行chip-package电源完整性分析的具体实现。     

基于布线轨道的SoC芯片供电带设计优化

针对传统用Synopsys公司IC Compiler工具自动生成供电带的设计方法会对布线资源产生一定程度的浪费,而影响物理设计布线质量的情况,提出了一种基于布线轨道的供电带设计优化方法。该方法在保证电压降的基础上,充分利用布线轨道,将供电带设计简化为两个参数的选取,同时推导出这两个参数与供电带占用布线轨道比例的关系公式,为后续设计流程留出足够的布线资源,提高芯片整体布线质量。将该方法用在一款采用TSMC 0.152μm Logic 1P5M CMOS工艺的电力载波通信芯片物理设计中,芯片数字规模约80万门。结果表明,在电压降保持稳定的情况下,释放了总共约300条布线轨道,为成功完成物理设计奠定了基础。     

DC-DC低功耗限流电路的设计

设计了一种用于升压型DC-DC转换器的限流电路,可以防止芯片内部的功率开关管遭受大电流的冲击。该电路把电流流过开关管产生的压降与参考电流流过参考管产生的压降相比较,输出电流限制信号,克服了传统限流电路功耗大等缺陷。还设计了一种低功耗的动态参考电流源,其软启动功能能够减小输出电压的过冲。Spectre仿真结果表明,限流电路有效限制了开关管的最大电流,满足设计要求。     

利用导通电压降监测SLD的输出光功率

由于传统的光功率采集仪精度不高,在实验中无法明显地显示出光功率在短期内的变化,而采集电压的数据采集系统可以很好地解决这个问题。在分析1310 nm超辐射发光二极管(Super Luminescent Diode,SLD)光源的工作原理的基础上,设计了一种在恒温条件下控制驱动电流来使SLD稳定工作的驱动电路,进行了理论分析和实验验证,给出了利用SLD电压降监测输出光功率的新方法,取得了真实可靠的实验数据。通过SLD光源的驱动实验得出输出光功率与驱动电流和SLD两端电压降的相关关系,结果表明,输出光功率与电流具有良好的线性关系,与电压具有良好的正相关指数关系。利用采集电压降监测SLD的输出光功率,大大提高了测试精度和数据分辨率,同时为SLD退化寿命试验提供了新的电学参数。     

基于聚酰亚胺介质的单平面微液滴驱动芯片

根据介电润湿(EWOD)原理,建立了电润湿力与驱动电压的关系,提出一种基于聚酰亚胺介质的单平面微液滴驱动芯片设计方案。该芯片利用MEMS技术在铬版玻璃上分别制作出金属微电极阵列和聚酰亚胺介质膜,再使用聚四氟乙烯分散液进行疏水处理,通过在电极阵列和微液滴之间直接施加电压以实现微液滴的驱动。对单平面微液滴驱动芯片的液滴介电润湿效应进行了仿真分析,结果表明仅使用疏水层便可观察到明显的介电润湿现象,接触角测量值与理论值吻合较好。使用该驱动芯片成功实现了微液滴的稳定传输,传输速度达到3.31 mm/s左右,并在实验基础上分析了传输速度与驱动电压幅值和频率的关系。     

LED尾灯动态转向功能失效分析及对策

通过分析LED尾灯动态转向功能失效原因,发现LED驱动芯片至LED灯组连线的天线效应是干扰信号的空间耦合途径;受干扰后,LED尾灯端口输出电压被拉低于故障检测电压,影响了LED尾灯的动态转向。经在LED驱动芯片输出端口处添加0.1μF电容并提高其故障检测的电压阈值,LED尾灯动态转向功能正常。     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

ASIC物理设计中金属层数对芯片的影响

ASIC芯片物理版图设计的一个重要问题是选用几层金属层。以一款SMIC0.18μmDVBC芯片(BTV2040S03)为例,选用三种不同金属层工艺进行对比。首先设计出三种不同金属层的版图,分析电源电势分布判断其合理性;之后进行布线拥塞率的对比,以分析不同金属层工艺对布线的影响;最后通过最终布线的时序验证和最终流片结果来证实选用金属层设计的可行性。通过上述方法研究集成电路物理设计中,如何选择所使用工艺的金属层数,以达到最大限度节约芯片成本、减小芯片面积和满足布线及时序的目的。     

IO单元自动排布算法IOAP

提出了一种应用于芯片物理设计过程中IO单元自动排布的新算法。IO单元排布是芯片物理设计过程中长期依赖经验的环节。IO单元排布的优化对布线,电源网格和设计收敛性的优化有很大贡献。文章重点研究边缘IO单元排布,提出了IO单元自动排布算法(IOAP)。此算法及其相关软件直接应用于视频解码芯片和无线传感器网络处理器芯片(已流片成功)的物理设计流程中。结果表明,IOAP有效改善了芯片的电源网格,时序和布线结果,减少了布线努力,提高了设计收敛性。     

P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter

In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation.

     

电子器件散热片换热特性的数值研究

对三种不同截面形状的散热片,在不同风速和相同加热功率下的换热特性进行数值模拟。得到三种散热片的底面芯片最高温度、传热系数以及压降在不同风速下的变化关系。通过对计算结果的分析可知：三种模型的底面芯片最高温度随着风速的增加而下降,传热系数和压降随着风速的增加而增大,这与相关实验数据的变化趋势一致。提高风速可以有效增强换热效果,但是压降的影响不容忽视。对比三种模型,收缩式散热片模型较另外两种模型具有换热效果好、压降小的优点,可为高热流密度的电子设备冷却方案的设计和改进提供参考。     

EWOD-based chip characterization under AC voltage

This paper addresses one basic issue of EWOD chip as a consumable: how to detect the alteration of hydrophobic layers? We investigate the possibility of using droplet oscillations to finely characterize chip ability to EWOD protocols. Experiments are performed in coplanar electrodes configuration. Dedicated setup and software have been developed for a simple in situ characterization. When a low-frequency AC voltage is used, drop surface oscillations are created from the time-varying component of the normal electrostatic stress at drop surface near the contact line. As an analysis tool, our software is based on droplet contour detection and delivers dynamical contact angle and contact line motion. Careful attention is brought to surface wetting or dewetting of the droplet during long-term AC actuation and surface ageing.     

基于各种快速Spice仿真器的Post-Layout寄生效应验证

现在的深亚微米工艺使用复杂的多层金属结构与先进电介质材料,随着工艺的进步,集成电路的器件尺寸越来越小,金属互连线做得越来越细,金属互连产生的寄生效应对电路性能的影响也越来越明显,各种各样的问题譬如由耦合电容产生了串扰噪声和延迟,IR drop引起的电压降,高电流密度引起的电迁移效应,以及混合信号设计中DC-path泄漏已经成为非常普遍的问题。对于整个芯片,在post-layout仿真时加上提取的寄生参数,有助于在设计中精确地分析每个寄生效应。快速Spice仿真器具有大的数据处理的容量和高的处理效率,因此这种仿真流程在设计中已经被广泛地应用。讨论如何在各种模式的仿真器(如UltraSim,NanoSim和HSIM)中选择合适的仿真器来进行post-layout仿真,以及不同的选择会有什么样不同的结果,另外还将对一些post-layout仿真结果进行分析。     

2D Mesh片上网络中交换机服务性能影响 的研究及其拓扑改进

 本文研究了交换机服务性能对2D Mesh片上网络的缓冲区资源和端到端延时的影响,发现在较低的丢包率的情况下,即使交换机能够提供很高的服务性能,却难以节省其所使用的缓冲区资源的现象.针对该现象,提出了一种基于星型子网的网状拓扑结构SSBM(Star-Subnet-Based-Mesh),在同样的网络规模以及丢包率的情况下,该种结构与2D Mesh结构相比具有更少的端到端通信延时,并且能够以较少的交换机服务性能为代价来节省较多的缓冲区资源,在较大程度上优化了2D Mesh片上网络的面积.     

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.     

Drop-shock reliability improvement of embedded chip resistor packages through via structure modification

We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.