Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 μA to 358 nA at 25 °C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process.     

Analog characteristics of metal-insulator-metal capacitors usingPECVD nitride dielectrics

The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency     

Review and Perspective of Architecture Development for Dynamic Random Access Memory

Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory（DRAM） applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor（Fin-FET）, Wafer bonded double gate and silicon on nothing（SON） gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/ silicon（PIS） capacitors to the metal/insulator/metal（MIM） capacitors used for today 50 nm technology node and below. In comparing Ta2O5 , HfO2 and Al2 O3 as high-k dielectric for use in DRAM technology, Al2 O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.     

Stability Improvement of 60 GHz Narrowband Amplifier Using Microstrip Coupled Lines

We present an analysis of microstrip coupled lines (MCLs) used to improve the stability of a 60 GHz narrowband amplifier. The circuit has a 4‐stage structure implementing MCLs instead of metal‐insulator‐metal (MIM) capacitors for the unconditional stability of the amplifier and yield enhancement. The stability parameter, U, is used to compare the stability of MCLs with that of MIM capacitors. Experimental results show that MCLs are more stable than MIM capacitors with the same capacitances as MCLs because the parasitic parallel resistances of MCLs are lower than those of MIM capacitors. Moreover, the bandwidth of an amplifier using MCLs is narrower than one using MIM capacitors because the parasitic series inductances of MCLs are higher than those of MIM capacitors.     

Modeling and optimization of series resistance of planar MIM capacitors

Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5 nF/mm²), but also a low series resistance R_s. The optimization of this latter parameter is investigated in this paper, by means of a simple analytical model, taking into account both the impact of material parameters and device architectures, suggesting possible strategies for R_s minimization. Such a model is also suitable for MIM circuit simulation, and can be also extended to other devices, such as to the gate series resistance modeling of RF MOSFET. Results are in good agreement with numerical simulations and HF measurements, performed on state of the art planar MIM devices. Moreover, discussion on via placement to access the top electrode has been held, in order to optimize the series resistance of the capacitor.     

Printable Ferroelectric PVDF/PMMA Blend Films with Ultralow Roughness for Low Voltage Non‐Volatile Polymer Memory

Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 10³ and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.     

An Analog Front‐End Circuit for ISO/IEC 14443‐Compatible RFID Interrogators

An analog front‐end circuit for ISO/IEC 14443‐compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a 0.25 µm double‐poly CMOS process. The fabricated chip was operated using a 3.3 Volt single‐voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single‐chip ISO/IEC 14443‐compatible RFID interrogators.     

A survey of circuit innovations in ferroelectric random-accessmemories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption     

Improvement of voltage linearity in high-/spl kappa/ MIM capacitors using HfO/sub 2/-SiO/sub 2/ stacked dielectric

It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C.     

Impact of Design on High-Frequency Performance of Advanced MIM Capacitors Using Si $_{3}$N $_{4}$ Dielectric Layers

High-frequency characterizations of ultra thin 32 nm PECVD Si$_{3}$N $_{4}$ dielectric in an advanced metal–insulator–metal (MIM) capacitors are presented, with focus on the impact of design on the performance of MIM capacitors. Frequency dependent capacitance has been extracted over a wide range of frequency bandwidth. An equivalent model circuit of capacitors including four parameters was developed to explain this behavior. The results have been compared with the values obtained from a 3-D electromagnetic modeling. A specific chart has been introduced to predict the electrical performance of new MIM capacitor designs.      

Printed Organic One‐Time Programmable ROM Array Using Anti‐fuse Capacitor

This paper proposes printed organic one‐time programmable read‐only memory (PROM). The organic PROM cell consists of a capacitor and an organic p‐type metal‐oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store “0.” Some organic PROM cells are programmed to “1” by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16‐bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with –50 V, and they are read out with –20 V. The area of the 16‐bit organic PROM array is 70.6 mm².     

Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory

The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO₂‐Al₂O₃‐ZrO₂/TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO₃, which has a dielectric constant of >100, even at a thickness ～10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO₂ and Al‐doped TiO₂ films might find space to fill the gap between ZAZ and SrTiO₃ MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO₂‐based dielectrics, which depends on having a dense, uniform and smooth RuO₂ layer as bottom electrode. Although the Ru (and RuO₂) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO₄ precursor made a thin, uniform, and denser Ru and RuO₂ layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO₃ films, grown at 370 °C, was ～150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO₃ film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.     

High-density chain ferroelectric random access memory (chain FRAM)

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F² size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V_dd cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation     

Quantum‐Tunneling Metal‐Insulator‐Metal Diodes Made by Rapid Atmospheric Pressure Chemical Vapor Deposition

A quantum‐tunneling metal‐insulator‐metal (MIM) diode is fabricated by atmospheric pressure chemical vapor deposition (AP‐CVD) for the first time. This scalable method is used to produce MIM diodes with high‐quality, pinhole‐free Al₂O₃ films more rapidly than by conventional vacuum‐based approaches. This work demonstrates that clean room fabrication is not a prerequisite for quantum‐enabled devices. In fact, the MIM diodes fabricated by AP‐CVD show a lower effective barrier height (2.20 eV) at the electrode–insulator interface than those fabricated by conventional plasma‐enhanced atomic layer deposition (2.80 eV), resulting in a lower turn on voltage of 1.4 V, lower zero‐bias resistance, and better asymmetry of 107.     

Intrinsic and extrinsic reliability of a serial connection of capacitors

The on-wafer serial connection of two capacitors (stacked capacitors) is attractive for two reasons: on one hand the intrinsic reliability and especially the immunity against high voltage pulses increases and on the other hand the early fail risk decreases tremendously. The intrinsic and extrinsic reliability of stacked capacitors are demonstrated using the example of a metal insulator metal capacitor (MIMCAP) with Al₂O₃ dielectric. The intrinsic reliability of a stacked capacitor, where each of the capacitors uses a dielectric of thickness thk, is equal to the intrinsic reliability of a single capacitor with twice the dielectric thickness 2 * thk. The reduction of early fails for a stacked capacitor is a probability effect: if a single capacitor has the probability p to fail early and an early fail of the stacked capacitor is the combination of two single capacitors each of which contains an early fail, then the stacked capacitor fails early with a probability of p². This basic idea is checked by voltage ramp experiments on single and stacked MIM capacitors, where the single MIM capacitors show besides the intrinsic branch a prominent extrinsic branch.     

Nanostructured metal–insulator–metal capacitor with anodic titania

This paper presents fabrication and electrical characterization of barrier type TiO₂ metal–insulator–metal (MIM) capacitor using anodization. Polarization process, conduction mechanisms, and structural properties are studied in detail. We found that the anodization voltage played a major role in electrical and structural properties of the thin film. The barrier type anodic TiO₂ is suggested as a dielectric material for high-performance MIM capacitors.     

一种新的铁电电容模型及其在1T/1C FeRAM中的应用

随着集成铁电工艺的迅速发展和铁电电容的广泛应用 ,铁电电容模型的缺乏已成为制约基于铁电电容电路设计和优化的瓶颈。文中提出的非线性双电容铁电电容模型是线性双电容铁电电容模型的改进 ,它不仅与线性双电容模型一样易于用宏模型实现 ,而且比后者具有更高的精度和更简单的控制方式。以 1 T/1 C单元作为基于铁电电容电路设计优化的实例 ,定性分析了位线寄生电容对读出窗口的影响 ,并在 HSPICE中用非线性双电容模型进行了仿真 ,得到位线寄生电容与 1 T/1 C单元铁电电容比例 (CBL/CF E)对读出窗口的最优值 :CBL/CF E=2 .4     

Experimental analysis of an MIM capacitor with a concave shield

A novel shielding scheme is developed by inserting a concave shield between a metal-insulator-metal (MIM) capacitor and the silicon substrate. Chip measurements reveal that the concave shield improves the quality factor by 11 % at 11.8 GHz and 14% at 18.8 GHz compared with an unshielded MIM capacitor. It also alleviates the effect on shunt capacitance between the bottom plate of the MIM capacitor and the shield layer. Moreover, because the concave shields simplify substrate modeling, a simple circuit model of the MIM capacitor with concave shield is presented for radio frequency applications.     

Incipient Ferroelectricity in Al‐Doped HfO2 Thin Films

Incipient ferroelectricity is known to occur in perovskites such as SrTiO₃, KTaO₃, and CaTiO₃. For the first time it is shown that the intensively researched HfO₂ thin films (16 nm) also possess ferroelectric properties when aluminium is incorporated into the host lattice. Polarization measurements on Al:HfO₂ based metal–insulator–metal capacitors show an antiferroelectric‐to‐ferroelectric phase transition depending on annealing conditions and aluminium content. Structural investigation of the electrically characterized capacitors by grazing incidence X‐ray diffraction is presented in order to gain further insight on the potential origin of ferroelectricity. The non‐centrosymmetry of the elementary cell, which is essential for ferroelectricity, is assumed to originate from an orthorhombic phase of space group Pbc2₁ stabilized for low Al doping in HfO₂. The ferroelectric properties of the modified HfO₂ thin films yield high potential for various ferroelectric, piezoelectric, and pyroelectric applications. Furthermore, due to the extensive knowledge accumulated by various research groups regarding the HfO₂ dielectric, an immediate relevance of ferroelectric hafnium oxide thin films is anticipated by the authors.