Microprocessor system buses: A case study

The system bus must provide a standard and stable interface for peripheral devices from different vendors, and to a large extent determines the system performance. Meeting often conflicting design goals of compatibility, interoperability, technology independence, and throughput requires careful consideration of bus parameters and design alternatives. This paper is a case study of seven microprocessor system buses: ISA, EISA, MicroChannel, VME, NuBus, FutureBus, and PCI. While we emphasize modern buses, such as VME64, FutureBus+, and PCI, the veteran ISA bus is still widely used and provides some perspective for discussion and comparison. We discuss bus protocols, throughput, synchronous and asynchronous bus design, Plug-and-Pay, and multiprocessor support. Throughout the paper the focus is on design principles and tradeoffs. As for future developments in the area of microprocessor system buses, we expect that enhancements of the PCI bus will solve problems not addressed by the current PCI 2.1 specification, such as the limited way in which PCI 2.1 supports the use of the bus during long latency transactions. Further development of PCI related standards will enable the use of PCI technology in industrial applications, embedded systems, laptops, and mobile systems.     

Performance analysis of BusNet protocol for backplane bus-based interprocessor communication

Nowadays, backplane bus-based multiprocessor systems often utilize the standard network protocol such as TCP/IP for communication between processors on the backplane bus. In such systems, it is common for the backplane bus to emulate the standard MAC protocols such as CSMA/CD. This paper aims to analyze the delay performance of the MAC emulation-based backplane network by constructing queueing models based on detailed bus operations. For this purpose, we choose BusNet as a target protocol. BusNet is an ANSI standard network protocol and its specification contains basic operations commonly used in most backplane buses. We investigate the throughput-delay characteristics in terms of packet size, block transfer scale, and arbitration scheme. We also compare the packet delay in BusNet with the IEEE 802.3 CSMA/CD network which BusNet is expected to be compatible with. The simulation result shows how an optimal block transfer scale can be determined in respect of the performance trade-off between BusNet and other real-time traffics.     

Computer system buses

A common bus, carrying information and electrical power between the various components of a digital system, is as important a part of the system as the microprocessor chip itself. The electrical properties of buses often cause design problems as insufficient attention is paid to them. This article deals with the properties of three types of bus line, considering the interfacing circuitry required by each type in detail.     

Robust planning of airport platform buses

Most airports have two types of gates: gates with an air bridge to the terminal and remote stands. For flights at a remote stand, passengers are transported to and from the aircraft by platform buses. In this paper we investigate the problem of planning platform buses as it appears at Amsterdam Airport Schiphol. We focus on robust planning, i.e. we want to avoid that the bus planning is affected by flight delays and in this way invokes delays in other flights and ground-handling processes. We present a column generation algorithm for planning of platform buses that maximizes robustness. We also present a discrete-event simulation model to compare our algorithm to a first-come-first-served heuristic as is used in current practice. Our computational results with real-life data indicate that our algorithm significantly reduces the number of replanning steps and special recovery measures during the day of operation.     

Multiplexed buses: the endian wars continue

The issue of data exchange between type-1 and type-2 buses, which multiplex the first data byte (which has the lowest address) with the least and most significant portions of the address, respectively, is considered. In an analogy based on Gulliver's Travels, the associated architectures have been dubbed little-endian and big-endian processors, respectively. It is pointed out that the byte order within integers and the byte order during transmission can differ. Therefore, the big and little adjectives are used to describe the order of bytes within integers, and the acronyms Mad and Sad to describe the order of bytes (most versus least important first) during transmission on a multiplexed address-data bus. After a review of the endian ordering issues, it is concluded that big- and little-endians can use the same bus standard. For high-performance serialized buses, the mad-endian order seems superior to a sad-endian order. For consistency between serialized and multiplexed parallel buses of various widths, the mad-endian order is proposed for future multiplexed standards. To minimize the interface costs to mad-endian buses, a big-endian order is proposed for shared data also     

数据均匀分布和正态分布的数据总线低功耗研究

低功耗设计已成为数字系统设计中必须考虑的问题,而总线低功耗设计是其中的重要分支。由于CMOS电路功耗的特性,降低总线上相邻两个传输数据状态的电压变化能有效降低总线功耗,降低总线翻转技术已成为降低总线功耗的重要研究领域之一,而Bus-Invert编码、ShiftInv编码是这一研究领域中的重要研究成果。以往的研究主要集中在遵从随机均匀分布的数据总线上,对该状态下的总线编码进行研究。由于总线上数据的相关性,现实中的总线数据往往服从正态分布的规律。通过对两种总线翻转编码技术的研究,得出对于服从均匀分布和正态分布的数据总线,ShiftInv编码技术降低功耗的能力均优于Bus-Invert编码技术。     

Embedding binary X-trees and pyramids in processor arrays withspanning buses

We study the problem of network embeddings in 2-D array architectures in which each row and column of processors are interconnected by a bus. These architectures are especially attractive if optical buses are used that allow simultaneous access by multiple processors through either wavelength division multiplexing or message pipelining, thus overcoming the bottlenecks caused by the exclusive access of buses. In particular, we define S-trees to include both binary X-trees and pyramids, and present two embeddings of X-trees into 2-D processor arrays with spanning buses. The first embedding has the property that all neighboring nodes in X-trees are mapped to the same bus in the target array, thus allowing any two neighbors in the embedded S-trees to communicate with each other in one routing step. The disadvantage of this embedding is its relatively high expansion cost. In contrast, the second embedding has an expansion cost approaching unity, but does not map all neighboring nodes in X-trees to the same bus. These embeddings allow all algorithms designed for binary trees, pyramids, as well as X-trees to be executed on the target arrays     

测控系统总线综述

综述了测控系统中机箱底板总线、计算机与测控系统的互连总线和现场总线的历史、性能、应用和发展。     

Reconfigurable buses with shift switching: concepts andapplications

We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of n bits can be computed in [log(n+1)/log w] broadcasts, each over n switches, assuming a global bus of width w. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant     

Assigning buses to schedules in a metropolitan area

The problem of scheduling a fleet of buses to a given set of trips is encountered by large bus companies performing thousands of trips per day. The time-tables for those trips are planned separately and reflect the passengers demand for transportation. These time-tables are inputs for the bus scheduling procedures. The scheduling problem is difficult due to its size and due to many operational constraints which are imposed. A mathematical formulation of the problem is presented and an efficient algorithm is developed. This paper presents results and computational experience that were obtained from implementing the model in a large bus company.     

Parking buses in a depot using block patterns: A Benders decomposition approach for minimizing type mismatches

In a transit authority bus depot, buses of different types arrive in the evening to be parked in the depot for the night, and then dispatched in the morning to a set of routes, each of which requests a specific bus type. A type mismatch occurs when the requested type is not assigned to a morning route. We consider the problem of assigning the buses to the depot parking slots such that the number of mismatches is minimized, under the constraint that the buses cannot be repositioned overnight. As in Hamdouni et al. [Dispatching buses in a depot using block patterns. Technical Report, Les Cahiers du GERAD G-2004-51, HEC Montreal, Montreal, Canada, 2004, Transportation Science, to appear], we seek robust solutions by assigning a block pattern to each depot. This pattern partitions the lane into at most two blocks, each block containing buses of a given type. Since it may not be possible to respect the selected block patterns, the problem also involves a second objective which is to minimize the discrepancy between the bus type assignment to the parking slots and the block patterns. In this paper, we first study the simplified case where only the second objective is taken into account. We model this simplified problem as an integer linear program and show that practical instances of it can easily be solved using a commercial MIP solver. Then we formulate the general case as an extension of the simplified model and propose to solve it with a Benders decomposition approach embedded in a branch-and-bound procedure. This procedure is required because the Benders decomposition yields a subproblem with integrality constraints. Of particular interests, we develop strong pruning criteria and an innovative branching strategy that imposes decisions on the master problem variables which already take integer values. Computational results for the general case are also reported.     

基于ZigBee的智能公交报站系统

设计一种基于无线ZigBee技术的智能公交报站系统,该系统利用ZigBee和3G无线通信技术能实现公交站台对公交车辆的到站预报功能,也能及时上报公交车辆运行大概位置信息,便于公交管理部门对公交车辆及时地进行管理、调度和维护。     

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated. Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities. A case study with the PAU for an H.264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations. This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC.     

Low Power Encoding Techniques for Dynamically Reconfigurable Hardware

In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.     

LXI总线及其关键技术研究

LXI总线是基于以太网技术的新一代测试总线技术。文章介绍了LXI总线诞生的背景,从主要功能、仪器标准、触发接口和编程技术几个方面分析了LXI总线技术的标准,比较了LXI总线和其他主流总线的性能,阐述了LXI总线在应用中的一些关键技术,最后对LXI总线在测控系统中的应用前景进行了展望。     

基于Linux系统的多种串行总线统一接口的实现

基于Linux字符设备操作接口和各类串行总线的共性,按照分层的思想,抽象出各种总线的统一接口。统一接口的应用层API与底层的具体总线操作形式无关,而且便于应用系统的升级和移植。文中给出了一种多种串行总线统一接口的实现方法,并以ARM9为平台,以I2C、1-Wire、SPI为例,验证了新方法的可行性。     

基于FPGA的BLVDS高速通信总线设计

测试总线是测试系统中的一个重要环节,是准确传输信号的关键。详细介绍了LVDS与BLVDS技术,在此基础上论述了BLVDS总线布置设计、PCB布线设计、数据格式设计及通信背板设计,并提出了一种基于FPGA的BLVDS总线设计,采用Verilog HDL实现FPGA内部逻辑电路设计,FPGA完成BLVDS总线上数据的接收、发送,以及数据的缓存。实验结果表明,该总线通信速度快、稳定、可靠。     

GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of the control bits, it finds partitions with similar transition behaviors and groups them together. One extra control bit is added to each group of partitions. Properly managing number of transitions on control bits of each partition and that of each group, GPH reduces total power consumption, including coupling power. It also locates control bits of each partition such that total power consumption is minimized. We evaluate the efficiency of the proposed method for coding data and address buses under various hardware platforms. Experimental results show 43% average power saving in coded data compared to the original one. We also show the prominence of our coding scheme over previously proposed techniques.     

Comparison of whole-body vibration exposures in buses: effects and interactions of bus and seat design

Bus and seat design may be important for the drivers' whole-body vibration (WBV). WBV exposures in buses during actual operation were assessed. WBV attenuation performance between an air-suspension seat and a static pedestal seat in low-floor buses was compared; there were no differences in WBV attenuation between the seats. Air-suspension seat performance in a high-floor and low-floor bus was compared. Relative to the pedestal seat with its relatively static, limited travel seat suspension, the air-suspension seat with its dynamic, longer travel suspension provided little additional benefit. Relative to the measurement collected at the bus floor, the air-suspension seat amplified the WBV exposures in the high-floor bus. All WBV exposures were below European Union (EU) daily exposure action values. The EU Vibration Directive only allows the predominant axis of vibration exposure to be evaluated but a tri-axial vector sum exposure may be more representative of the actual health risks.     

Ambulant disabled persons using buses: experiments with entrances and seats

This paper describes research work carried out in Sweden to adapt buses to the requirements of ambulant disabled people. It contains an experimental study where subjects tried different entrances and seats. For the experiments a bus was rebuilt and equipped with new entrance and seating arrangements. Three categories of subjects participated: seriously ambulant disabled, representing people having severe ambulatory difficulties in their daily life; less seriously ambulant disabled, representing people that normally travel with the special transportation service; and slightly ambulant disabled, representing ordinary elderly people. The evaluation was based on observations, photographs, interviews and in some cases timing with a stopwatch. The results show that low similar steps and well-designed handrails in the bus entrance made boarding and alighting easier. The seat trials showed the importance of having suitable grab rails to allow people to pull or heave themselves up. Design requirements are presented in the paper. The Swedish Board of Transport have used the results when working out regulations to adapt public transport vehicles for use by disabled people.