I~2C串行总线及其软件接口

介绍了Ｉ２Ｃ串行总线的操作时序和数据结构，并以串行Ｅ２ＰＲＯＭ与不具有Ｉ２Ｃ总线接口的单片机连接为例，用软件实现Ｉ２Ｃ串行总线接口。     

SPI总线接口扩展与应用

在众多型号的单片机中,有许多不带SPI串行总线接口,从而限制了其对SPI总线接口器件的使用.本文介绍了SPI串行总线的特征和时序,对无SPI总线接口的单片机采用其I/O端口,通过程序控制的方法,模拟SPI串行总线接口,使其能与SPI总线接口的器件之间进行数据传送,并以串行E2PROM应用为例,介绍了模拟SPI串行总线接口的使用方法.     

基于VHDL/CPLD的I~2C串行总线控制器设计及实现

分析了I2C串行总线的数据传输机制,用VHDL设计了串行总线控制电路,其中包括微处理器接口电路和I2C总线接口电路。采用ModelSimPlus6.0SE软件进行了前仿真和调试,并在XilinxISE7.1i开发环境下进行了综合、后仿真和CPLD器件下载测试。结果表明实现了I2C串行总线协议的要求。     

SPI串行总线在8031单片机应用系统中的实现

ＭＣＳ５１系列、ＭＣＳ９６系列、ＡＴＭＥＬ８９系列等单片机应用很广,但它们均没有ＳＰＩ串行总线接口,限制了在这些系统中使用具有ＳＰＩ总线接口器件的应用。本文将介绍ＳＰＩ串行总线的性能,并以串行Ｅ２ＰＲＯＭ为例,给出了在８０３１单片机上利用Ｉ／Ｏ线实现ＳＰＩ串行总线的方法和软件设计。     

I2C串行总线在单片机8031应用系统中的设计与实现

目前,ＭＣＳ５１系列、ＡＴＭＥＬ８９系列、６８ＨＣ０５系列等单片机应用很广,但他们均没有Ｉ＾２Ｃ总线接口,限制了在这些系统中使用具有Ｉ＾２Ｃ总线接口器件的应用。本文将介绍Ｉ＾２Ｃ串行总线的性能,并以串行Ｅ＾２ＰＲＯＭ为例,给出在８０３１上利用Ｉ／Ｏ线实现Ｉ＾２Ｃ串行总线的方法和软件设计。     

基于C8051F的数据传输系统设计与实现

在简要介绍I2C总线特点的基础上,扼要介绍了C8051F系列单片机的SMBus串行总线的接口结构及工作原理,重点阐述了利用C8051F单片机串行总线接口设计的高功率放大器监控系统中数据传输系统的硬件和软件设计,给出了电原理图和软件流程图.     

基于电池能源管理芯片Bq2060的SMBus总线编程

Bq2060作为一种智能电池能源管理芯片,广泛应用于笔记本电池管理系统中。它具有SMBus高效同步串行总线通讯接口功能,通过SMBus串行总线和系统进行通讯,可检测电池信息包括剩余容量、总容量、在现有放电速率下的剩余时间、充电电压等信息。介绍了基于Bq2060的SMBus串行接口的智能电池监测系统,利用SMBus接口和内嵌的智能电池状态监测系统进行实时检测,通过操作系统调用电池芯片内部指令进行智能控制,在分析其通讯协议的基础上,分析了SMBus总线编程配置和操作特点。     

SPI串行总线在单片机8031应用系统中的设计与实现

ＭＣＳ５１系列,ＡＴＭＥＬ８９系列等单片机应用很广,但他们没有ＳＰＩ串行总线接口品,限制了在这些系统中使用具有ＳＰＩ总线接口器件的应用,本文将介绍ＳＰＩ串行总线的性能,并以串行Ｅ＾２ＰＲＯＭ为例,给出了在８０３１上利用Ｉ／Ｏ线实现ＳＰＩ串行总线的方法和软件设计。     

基于USB和便携式医疗设备的数据采集系统实现

通用串行总线(USB)作为一种崭新的微机总线接口规范,具有传输速度快、可靠性高、易于连接等特点,非常适合作为主机和医学仪器之间的通讯接口。文章介绍了USB总线接口芯片CH375并在此基础上实现了PC机与便携式医疗设备医学信号的实时数据采集和传输,给出了相关的程序代码。     

无线USB接口键盘控制器的设计

通用串行总线USB是一种崭新的微机总线接口规范.本文介绍了一种基于USB接口的无线通讯键盘控制器的设计方案,包括硬件设计、设备驱动程序设计及应用软件设计.     

Integrated bus transit scheduling for the Beijing bus group based on a unified mode of operation

This paper presents an applied study of scheduling buses and drivers for the Beijing Bus Group (BJBUS), the largest bus company in China. This is pioneering research in China for bus transit scheduling using computers based on a unified mode of operation. It is anticipated that the research fruits and experiences obtained would be of benefit to other bus operators in China. The bus transit scheduling problem in BJBUS is first presented in the paper. The particular characteristics are pointed out, which are different from those in developed countries, while many are common in China. After a brief review and analysis of the appropriateness of some currently successful approaches, the paper focuses on reporting the solution ideas and methods for BJBUS, especially those developed to solve the specific problems of BJBUS, such as scheduling buses with built-in meal periods, multi-type bus scheduling, restricting drivers to one or two particular buses, etc. Finally, the implementation and computational results are reported before the concluding remarks.     

双FIFO的LBE总线与Avalon总线的接口系统设计

为了实现 LBE总线与 Avalon总线设备之间跨时钟域数据交换,设计了桥接在两种总线间的接口 IP 软核.利用Verilog硬件描述语言的层次化设计方法,设计了接口IP核的底层模块,其中包括命令FIFO模块、状态FIFO模块、LBE总线端接口模块和 Avalon总线端接口模块.在FPGA硬件平台上,进行两种总线间的双向数据传输实验.结果表明,采用双FIFO的 LBE总线与 Avalon总线接口系统满足设计要求,能够实现数据的稳定可靠交换.     

基于DSP的CAN总线转换器的设计

阐述了一种以TMS320LF2407A为核心，RS232、RS485和CAN总线之间接口和协议转换的设计方案，实现了这几种通用的串行总线之间的通信；叙述了总线转换器的功能、硬件设计、通信协议和软件设计。总线转换器的通信网络接口为多种异型总线之间的互联和构建比较复杂的总线型网络提供了一种解决方案。     

Evolving buses: backplane buses mature to keep pace with technology

Considers how the role and importance of the backplane bus in a system has evolved along with the advances in technology over the past decade. Backplane buses have come a long way from the early days of fairly simple protocols, a couple of connectors, and some traces on a printed circuit board. In early bus-based systems, the backplane bus was the main system bus providing interconnects from the CPU to memory, I/O, peripherals, and networking. The bus interface alone could easily take up a third of the board real estate on a small card. In today's systems, however, advances in technology and packaging art having a significant effect on what is expected of a backplane bus. Yesterday's backplane buses can no longer keep up with the demands of today's high-performance CPUs and their interconnection requirements. What we need is a new generation of buses to meet the expanded needs     

基于CPLD的计算机接口电路设计技巧

本文介绍了利用计算机ISA、PCI总线和打印机接口设计密码电路，基于CPLD设计密码电路，具有加密性能好的特性，通过并行打印机接口设计一个密码电路，密码存储在电路中，通过操作接口读取密码，ISA总线可以直接读取电路密码。PCI总线可以通过W89C940af对密码电路进行操作，读取设置密码。     

电子测试仪器的发展趋势

论述了几种典型的测量仪器接口总线,分析了它们的主要特点及与计算机总线的联系,并综述测量仪器与计算机进一步紧密结合,形成新一代自动测试系统这一必然的发展趋势。     

USB2．0-ATA桥接器IP核设计

USB2.0为PC外设中的大容量存储设备提供了很好的支持,出现了一系列的便携式大容量存储设备.大容量存储设备遵循不同于USB2.0协议的ATA协议,因此需要在两个总线之间设计一个USB2.0-ATA桥接器来进行指令翻译和数据管理.本文设计了一种USB2.0-ATA桥接器IP核,为内嵌ATA接口的USB设备开发打下基础,并可用于SOC的集成中.     

基于XML的统一通信业务接口研究及应用

文章针对通信业务接口不统一,不具备可扩展性,不能适应目前业务种类的多变以及通信手段更新迅速等问题,提出了基于XML的对通信业务接口进行统一描述的解决方案,并结合语音接入平台给出了相应的应用实例。     

Multiplexed buses: the endian wars continue

The issue of data exchange between type-1 and type-2 buses, which multiplex the first data byte (which has the lowest address) with the least and most significant portions of the address, respectively, is considered. In an analogy based on Gulliver's Travels, the associated architectures have been dubbed little-endian and big-endian processors, respectively. It is pointed out that the byte order within integers and the byte order during transmission can differ. Therefore, the big and little adjectives are used to describe the order of bytes within integers, and the acronyms Mad and Sad to describe the order of bytes (most versus least important first) during transmission on a multiplexed address-data bus. After a review of the endian ordering issues, it is concluded that big- and little-endians can use the same bus standard. For high-performance serialized buses, the mad-endian order seems superior to a sad-endian order. For consistency between serialized and multiplexed parallel buses of various widths, the mad-endian order is proposed for future multiplexed standards. To minimize the interface costs to mad-endian buses, a big-endian order is proposed for shared data also     

Hierarchical message bus-based software architectural style

As the size and complexity of software systems increase, the design and specification of overall system structure become more significant issues than the choice of algorithms and data structures of computation. An appropriate architecture for a system is a key element of its success. Based on the practice of Jadebird software production line, this paper proposes a software architectural style based on hierarchical message buses, named JB/HMB. In this style, the component model consists of external interfaces, static structure and dynamic behavior, which depicts a component from different aspects. Supported by message buses, components interact with one another by messages, which can be used to describe distributed and concurrent systems well. JB/HMB style supports stepwise decomposition and refinement, and runtime system evolution. Finally, characteristics of JB/HMB style are summarized as a conclusion, and future research directions are specified.