Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

In situ measurement of wafer temperatures in a low pressurechemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer     

Analyses of thermal stresses and control schemes for fasttemperature ramps of batch furnaces [IC manufacture]

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

熔石英玻璃激光损伤的三维应力场研究

为了研究CO₂激光损伤后熔石英玻璃内部的三维应力场分布,采用脉冲CO₂激光与熔石英玻璃相互作用的有限元数值模型,计算了脉冲激光停止时熔石英玻璃内部的温度分布,并研究了材料冷却后的内部三维应力分布和表面初始损伤形貌,计算结果与实验结果吻合。以该模型为基础,详细分析了径向和环向应力的三维分布,结果表明,在损伤凹坑附近,径向应力表现为压应力,且在凹坑底部附近取得最大值后,径向应力沿深度方向逐渐转化为拉应力;损伤凹坑附近的环向应力与径向应力相似,均表现为压应力,但压应力沿径向逐渐转化为拉应力,不同深度处的环向应力沿轴向增至最大后逐渐减小。另外,脉冲激光能量的增大导致径向应力与环向应力及其影响范围均有明显增加。研究结果有助于分析激光损伤熔石英玻璃内部的三维应力场,为CO₂激光修复工艺的改进提供了理论依据。     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Temperature distribution in semiconductor wafers heated in ahot-wall-type rapid diffusion furnace

Transient temperature distribution was calculated for wafers heated in a new hot-wall-type rapid diffusion furnace. Two-dimensional radiative heat transfer was combined with unsteady conduction in wafers and the furnace. The furnace is composed of parallel plate heaters, and heats wafers to a temperature of about 1000°C. The heaters are divided into four zones and their heating powers are PID-controlled. Two wafers on a holder are inserted vertically from the bottom of the furnace, and heated for three minutes. The calculated results show the wafer temperature approached the desired heating temperature about one minute after insertion, agreeing with experimental results. The average temperature distribution in the wafers during heating is found to be within ±1°C at 1000°C, when the heating power (temperature) of the four zones is properly controlled. The effects of heater temperature, insertion speed, and holder thickness on the temperature distribution in wafers were calculated. The new hot-wall-type rapid diffusion furnace can be used to manufacture future VLSI     

Sources and transport mechanisms of gaseous impurities in verticalthermal reactors

This work focuses on the different mechanisms of impurity transport and distribution in process equipment, with particular emphasis on moisture distribution in vertical thermal reactors. The results are important in both control and metrology of gaseous impurities during startup and process cycles. In addition to direct measurements, a comprehensive theoretical model is developed which is useful for process parametric study to optimize the process parameters or improve the reactor design. The results show that the impurity purge during startup is controlled by the diffusion in the wafer spacing; this diffusion becomes a bottleneck for large wafers and high furnace loading. The major sources of impurities during the wafer introduction (wafer push) stage are backdiffusion, impurity diffusion from the wafer spacing and outgassing of wafers as they enter the reactor. The primary sources during operation are permeation through the quartz reactor walls and leakage, together with backdiffusion, from the furnace outlet gaskets. A constant source of impurity is permeation through the polymeric tubing and fittings commonly used on the inlet side of the furnace. The kinetics and the mechanisms of each of these sources are determined through a combination of experimental measurements and process simulation     

Effect of residual stress on critical current density of YBa2Cu3O7−x thick films

YBa₂Cu₃O_x films were fabricated on 10-cm-diameter polycrystalline MgO wafers by spray pryolysis of a metal acetate solution. In-plane residual stress of the films was obtained by shadow Moiré interferometry and correlated with crack formation and critical current density. High tensile stresses (0.96 GPa) were measured at the wafer center and decreased toward the edge, which corresponded with the largest number of cracks and lowest critical current density at the wafer center. A major cause of the residual stress (0.5 GPa) was caused by a tetragonal-to-orthorhombic phase transition in YBa₂Cu₃O_x.     

高温退火对铸造多晶硅片中位错密度的影响

对铸造多晶硅片进行了1 000~1 400℃的高温退火和不同方式冷却实验,用显微观察法对退火硅片及其相邻姊妹片位错密度进行了测量统计。研究了退火温度和冷却方式对铸造多晶硅片中位错密度的影响。结果证实:当退火温度在1 100℃及以下时,硅片的位错密度并没有降低反而增加了;当退火温度在1 320℃及以上时,硅片的位错密度明显降低,其幅度随温度提高增大;但退火后如断电随炉冷却而不控制冷却速率,位错密度又会提高。     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

高功率掺镱双包层光纤激光器热效应理论研究

针对高功率双包层光纤激光器热效应严重制约着光纤激光器的输出功率和光束质量这一现象,利用热传导方程和边界条件推导出了双包层光纤激光器温度分布的解析解,进而分析了热效应引起的应力分布,温度和应力引起的折射率变化以及热效应引起的光程差。结果表明,在纤芯轴线处切向、法向、轴向应力分别达到负的最小值,而在光纤表面处径向应力为0,法向、轴向达到正的最大值;应力引起的折射率变化与温度引起的折射率变化相比较小;温度变化是热效应引起光程差主要原因,热膨胀和热应力引起的光程差较小。     

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

晶片键合界面应力分布的理论分析

根据双金属带的热应力分布理论,推导了晶片键合以及薄膜键合的界面应力分布公式.对影响晶片键合的剪切应力、正应力以及剥离应力的分布特性进行了讨论