Selection of Voltage Thresholds for Delay Measurement

Since all physical devices have a finite non-zero responsetime, the notion of delay between the input and output logicsignals arises naturally once digital abstraction is done. Thisdelay should be positive and non-zero, since a physical devicetakes a finite amount of time to respond to the input. Defininga strictly positive delay is not a problem in the abstract domainof logic signals, since input and output events are preciselydefined. However, when the signal non-idealities are accountedfor, the notion of events is blurred and it is not obvious howto define delay such that it reflects the causal relationshipbetween the input and the output. By necessity, we define thestart and end points of these events by determining the timeinstants when the signals cross some appropriate voltage thresholds.The selection of these voltage thresholds for logic gates aswell as simple interconnect wires, is the subject of this paper.We begin by a discussion of what we mean by signal delay andhow it arises in a logic gate. With this background, startingfrom ideal inputs to ideal inverters and concluding with physicalinputs to physical inverters, we examine the problem of thresholdselection for inverters through a logical sequence of model refinement,using a combination of analytical and experimental techniques.Based on the insight gained through this analysis, we examinethe problem for multi-input (both static and dynamic) gates aswell as point-to-point interconnect wires. We show that thresholdsderived from the gates DC voltage transfer characteristic removesthe anomalies, such as negative delay and large sensitivity toinput waveshape effects, that can arise with the widely used50% and 10%–90% thresholds. Despite its fundamentalnature, however, we note that the problem of threshold selectionhas received scant attention in the literature. To the best ofour knowledge, this is the first detailed study of this problem.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

Theory of PLL fractional-N frequency synthesizers

This paper presents an overview of the evolution of frequency synthesizers based on phase-locked loops (PLLs). The main limitations of the digital PLLs are described, and the consequent necessity of using fractional-N techniques is justified. The origin of the typical spurious noise lines on the sidelobes of the synthesized frequency is explained. It is shown how to eliminate these spurious noise lines by using digital modulators to control the frequency division value. Finally, the implications of using digital modulators together with fractional-N PLLs on the output phase noise are analysed.     

Frequency Performance Compensation of Operational Amplifiers with the ‘T’ Feedback Network

A simple T network can be used in the feedback path of a conventional voltage feedback operational amplifier (VFOA) to avoid using a large feedback resistor. However detailed analysis shows that the bandwidth of amplifier will be degraded. In this paper, a capacitive compensation method for the T network is described which yields a significant improvement in closed-loop bandwidth of the amplifier.     

On Hautus-type conditions for controllability of implicit linear discrete-time systems

Four notions of controllability for general (i.e., possibly nonregular) implicit linear discrete-time systems are considered. Relationships between them are studied. A Hautus-type characterization of all of these notions is also given.This work was performed under the auspices of RP.I.02: Teoria sterowania i optymalizacji ciagych ukadów dynamicznych i procesów dyskretnych.     

A 4 GHz ΔΣ Fractional-N Frequency Synthesizer

A 4 GHz fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 m BiCMOS process. The synthesizer achieves a close-in phase noise of –66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH -modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.     

A Direct Digital Synthesizer with Tunable Delta Sigma Modulator

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma () modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1-bit D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.     

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 m×221 m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).     

Oversampling ΣΔ Analog-to-Digital Converters Modeling Based on VHDL

The paper presents a VHDL model of an oversampling analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.     

A 1-V 15 μW High-Accuracy Temperature Switch

A CMOS temperature switch with uncalibrated high accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 m CMOS process. The temperature switch has an in-designed hysteresis of 1.2°C around a threshold value of 128°C. At the switching-threshold all matched transistors have also matched operating conditions, yielding a temperature threshold that is highly independent of transistor output resistance and supply voltage. The chip area was minimized using a novel and generic strategy. With a chip area of only 0.03 mm², the onwafer 3 spread of the threshold temperature is 1.1°C. Power consumption is only 15 A at 1 volt supply.     

An RF Power Amplifier in a Digital CMOS Process

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 load. A design method to find the large signal parameters of the output transistor is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3/8-8PSK) modulated signal.     

Editorial

Future integrated microsystems will benefit significantlyfrom progress in the VLSI field. Two key elements will boostthe implementation of new micro-integrated architectures: progressin batch-manufactured silicon sensors and the introduction ofnew circuit techniques for designing interface circuits. Thesetwo factors will be essential in favoring the transition fromthe present research driven speculations to customer drivenactivities. This paper discusses the key issues in realizingmicrosensors and the most suitable circuit techniques for interfacingand processing their output signals. A number of examples ofintegrated structures will illustrate present problems and possiblesolutions.     

Redundancy Removal during High-Level Synthesis Using Scheduling Don‘t-Cares

Previous work in automata theory has shown how to eliminate sequential redundancy from networks of FSMs by finding sequences of inputs and outputs which are never communicated between components of the network. This paper shows that behavior automata—finite-state machines whose inputs and outputs are incompletely scheduled—exhibit similar properties. Using the behavior FSM (BFSM) as a model for scheduling, we show how to identify and eliminate both input and output scheduling dont-cares. When a scheduling dont-care is eliminated from a network of BFSMs, the register-transfer implementation is guaranteed not to suffer from the corresponding dont-care sequence. A definition of scheduling dont-cares improves our understanding of the foundations of high-level synthesis and the relationship between high-level and sequential optimization. In practice, scheduling dont-care elimination is a powerful tool for eliminating redundancy early in the design process.     

A General Approach for Image and Co-Channel Interference Suppression in Diversity Wireless Receivers Employing ICA

In this contribution, a general approach to suppress image signal and co-channel interference in a wireless receiver is presented. The technique employs diversity reception, and the algorithm is based on complex-valued independent component analysis (ICA). The proposed ICA method increases the channel capacity through greater frequency reuse, and it simplifies the receivers front end by eliminating the need for analog image filtering. Also, the new technique is computationally efficient and has attractive implementation features in terms of the requirement for A/D converters speed and bandpass filters selectivity. Simulation results show that the performance is robust over a wide range of input signal-to-interference ratios, and the algorithm has fast convergence.     

Wireless telecom silicon integration: analog design for radio,baseband and speech spectrum

The application today, pushing analog design for CMOS and RFbipolar into new frontiers is definitely the mobile radio telephony. New telecom systems like GSM, PCN, DECT, DCS, Wireless in the loop ... are all developing very rapidly and will enable us very soon to organise a complete telephone network with full coverage for your car, as well as in your kitchen and on your office desk. In Europe the major telecom companies have worked together to establish one common standard for cellular mobile radio communications at 900 MHz. Similar things are happening for other wireless personal communication systems. Basically the cellular radio telephone, the wireless PABX and the wireless SLIC are bringing the same challenges to analog circuit design: maximum integration of the basic radio functions into 1 or 2 silicon chips, CMOS, Bipolar or BiCMOS or GaAs. The analog circuit designer for radio telephone applications will need all the state of the art analog design knowhow available today, from RFmixers and GHz range low noise amplifiers and local oscillator synthesizers over base band 100 kHz CMOS analog to low frequency speech analog to digital conversion. And for all these circuits the message is: minimum power consumption for battery autonomy, minimum silicon area for maximum functional integration per die to obtain a small, low cost pocket size radio telephone.