Comparison of high impedance input topologies with low EMI susceptibility

Different Input Topologies with resistance to electromagnetic interferences (EMI) are analyzed and compared in terms of EMI reduction. The emphasis in this study is put on circuit robustness and applicability to industrial applications, which requires sufficient EMI rejection over all process corners. Furthermore, a new topology based on a replica amplifier is introduced, that is more robust to process variation compared to previous works (Jean-Michel Redouté and Michiel Steyaert, ESSCIRC, Sept. 2008; Fiori, IEEE Transac Electromag Compat 49(4):834–839, 2007) that rely on accurate matching of absolute values in order to achieve efficient EMI cancellation.     

Design Considerations for Cascade $Delta Sigma $ ADC's

This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter.     

A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.     

Improved EMI filtering current mirror structure requiring reduced capacitance

The design of an improved current mirror is described, capable of filtering conducted electromagnetic interference without causing charge pumping. One of the major advantages of this structure lies in the reduced capacitance needed to realise the filter function, making this circuit perfectly suitable to use in an integrated environment.     

Measurement of EMI induced input offset voltage of an operational amplifier

An efficient measurement technique is introduced for determining the input referred offset voltage induced by electromagnetic interference (EMI) in operational amplifiers.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

An Analytical Approach to Obtain the Interdeparture Time Characteristics in a Multistage VoIP Network

In this paper, we investigate the evolution of the interarrival and interdeparture times between voice packets when they are proceeding through a number of network nodes. We model the arrival process in a node as the superposition of a single tagged stream and an independent background process that aggregates the remaining traffic sources. Because we assume that the load of a single voice stream is very low compared to the load of the aggregate traffic, we can represent the tagged voice packets as markers (packets with size zero). We will establish an expression for the probability generating function (pgf) of the interdeparture time of the voice packets after one stage and use this interdeparture-time pgf as the pgf of the interarrival time of the voice packets in the next stage, in order to assess the evolution of the interarrival-time characteristics throughout the network.     

Heavy Ion Development at the Berkeley 88-Inch Cyclotron

A new internal Penning ion source is now being tested for production of nitrogen and oxygen beams. Nitrogen beams of N5+ have been accelerated to 250 MeV. An external source for lithium beams is being developed.