Tantalum-gate thin-film SOI nMOS and pMOS for low-powerapplications

The threshold voltages of thin-film fully-depleted silicon-on-insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta) as the gate materials. Ta-gate FDSOI MOSFET's have excellent threshold voltage control for 1.0 V application on low impurity concentration SOI layers in both nMOS and pMOS. The low-temperature processing after the gate oxidation step leads to good on/off characteristics in Ta-gate SOI MOSFET's because of no reaction between Ta gate electrode and SiO₂ gate insulator. This technology makes it possible to drastically decrease the number of the process steps for CMOS fabrication, because the same gate material is available for both nMOS and pMOS     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

纳米CMOS器件中源/漏串联电阻栅长相关性研究

本文利用恒定迁移率、直接Id-Vgs和Y函数三种方法对纳米CMOS器件中提取的源/漏串联电阻(Rsd)与器件栅长(L)相关性进行了研究。结果表明,采用恒迁移率方法得到的Rsd具有与栅长无关的特性,纳米小尺寸CMOS器件的Rsd值在14.3Ω~10.9Ω之间。直接Id-Vgs和Y函数方法都得到了与L相关的Rsd值,误差分析发现从直接Id-Vgs和Y函数两种方法中提取的Rsd对L依赖性与提取过程中的栅极电压导致有效沟道迁移率(μeff)降低有关,推导过程中忽略了这种影响,Rsd值叠加了一个与栅长相关的量。本文计算了这个叠加的误差值,并得到消除此误差值之后各个栅长器件的Rsd值。     

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40 nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.     

Extracting the series resistance and effective channel length of short-channel MOSFETs at liquid nitrogen temperature

We present a simple method to extract the effective channel length and the gate voltage dependent series resistance of p-channel MOSFETs. The method is used at room and at liquid nitrogen temperatures on devices with mask channel lengths in the range of 0.6–2.0 μm. The good agreement found at 77 and 300 K between the experimental drain current-voltage characteristics of the devices and those computed from the extracted parameter verifies the validity of the method.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

Analog circuits based on the subthreshold operation of CMOS devices are very attractive for ultralow power, high gain, and moderate frequency applications. In this paper, the analog performance of 100 nm dual-material gate (DMG) CMOS devices in the subthreshold regime of operation is reported for the first time. The analog performance parameters, namely drain-current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), early voltage (V_A), output resistance (R_o) and intrinsic gain for the DMG n-MOS devices, and and for the DMG p-MOS devices are systematically investigated with the help of extensive device simulations. The effects of different capacitances on the unity-gain frequency are also studied. The DMG CMOS devices are found to have significantly better performance as compared to their single-material gate (SMG) counterpart. More than 70% improvement in the voltage gain is observed for the CMOS amplifiers when dual-material gates, instead of single-material gates, are used in both the n- and p-channel devices.     

Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

In this paper, we review different CMOS technologies used at CEA-LETI to improve hole and electron velocity for the 32 nm technology node Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs. The orientation, the strain and the material of the channel are the key parameters that have been tuned and optimized. Tensile strained SOI (sSOI) for nMOS and compressive Ge for pMOS are found to be promising channels for CMOS integration. They provide a 2 times (7.5 times) mobility improvement for electrons (holes), giving rise to well-balanced drain currents for n and pMOS. They also allow a tuning of the threshold voltage. The gate length and width scalabity of these technologies are also addressed. In particular, we detail the excellent performance of strained Si_0.6Ge_0.4 and sSOI down to 30 nm gate length. We also discuss the specifics of short channel transport in these channels: the role of the carrier mobility, the limiting scattering phenomena and the ballistic transport.     

Investigations of Key Technologies for 100V HVCMOS Process

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

100V高压CMOS工艺关键技术的研究

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Fabrication and Performance of 0.25-$mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f_max of 47 GHz have also been measured.