用于MFIS的铁电薄膜刻蚀技术研究

制备ＭＦＩＳ存储器的铁电薄膜一般选用抗疲劳特性好的ＳＢＴ铁电薄膜,介质层一般选用ＺｒＯ２作为阻挡层,以克服电荷注入效应,改进器件的性能。在ＭＦＩＳ研制中,ＳＢＴ薄膜和ＺｒＯ２薄膜的刻蚀是关键工艺之一。研究了用ＳＦ６和Ａｒ作为反应气体刻蚀ＳＨＢＴ及ＺｒＯ２薄膜的方法,对不同条件下ＳＢＴ和ＺｒＯ２的刻蚀速率进行了实验研究和讨论、分析,得到了刻蚀ＳＢＴ及ＺｒＯ２的优化工艺条件。     

TFT工艺中的反应性离子刻蚀

对ＴＦＴ器件工艺中的反应性离子刻蚀技术进行了研究,给出了ＴＦＴ器件工艺中常见薄膜刻蚀速率的实验结果,并讨论了掺杂气体（如Ｈ２、Ａｒ等）对刻蚀速率的影响。     

金刚石薄膜的反应离子刻蚀

反应离子刻蚀是金刚石薄膜图形化的一种有效方法。研究了用Ｏ２及与Ａｒ的混合气体进行金刚石薄膜图形化刻蚀的主要工艺参数（射频功能、工作气压、气体流量、反应气体成分与比例等）对刻蚀速率和刻蚀界面形貌的影响，兼顾刻蚀速率和刻蚀平滑程度等关键因素，建立了金刚石薄膜刻蚀的优化工艺参数，达到了较满意的图形效果。     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。     

Sol-Gel法制备的铁电薄膜和Pt/Ti下电极的反应离子刻蚀技术

为制备Ａ１／ＰＺＴ／Ｐｔ／Ｔｉ电容,研究了采用ＳＦ６／Ａｒ等离子体对Ｐｂ（Ｚｒ,Ｔｉ）Ｏ３及Ｐｔ／Ｔｉ底电极进行反应离子刻蚀（ＲＩＥ）的技术．较系统地研究了ＲＦ功率,ＳＦ６／Ａｒ流量比及气压对刻蚀速率的影响,找到了对ＰＺＴ及Ｔｉ进行ＲＩＥ的优化工艺条件．在不同的条件下得到对ＰＺＴ的刻蚀速率为２～７ｎｍ／ｍｉｎ;采用纯Ａｒ气体时Ｐｔ的刻蚀速率为２～６ｎｍ／ｍｉｎ;对于Ｔｉ可用ＨＣｌ及Ｈ２Ｏ２溶液进行腐蚀     

一种新的硅深槽刻蚀技术研究

本文报告了一种获得侧壁陡直的硅深槽新技术．实验中采用一种新材料──氮化锆（ＺｒＮ）作为反应离子刻蚀的掩模，所需掩模厚度约５００．采用氟基气体ＳＦ６作为刻蚀气体，并附加Ａｒ和Ｏ２，这样刻蚀过程中在槽的侧壁会形成氧化硅作为阻挡刻蚀层，结果得到了深约６μｍ，侧壁垂直接近９０°的硅深槽．     

亚微米光刻与刻蚀工作研究

采用三层胶光刻工艺以及ＳＦ６＋Ａｒ为反应气体的反应离子刻蚀工作，实现了小于０．５０μｍ的图形转移，并将此微细加工工艺应用于０．５０μｍＣＭＯＳ集成电路的制做。     

亚微米光刻与刻蚀工艺研究

采用三层胶光刻工艺及以ＳＦ＿６＋Ａｒ为反应气体的反应离子刻蚀工艺，实现了小于０．５０μｍ的图形转移，并将此微细加工工艺应用于０．５０μｍＣＭＯＳ集成电路的制做。     

SF_6／CCl_2F_2反应离子深刻蚀硅中加O_2的研究

用ＳＦ＿６／ＣＣｌ＿２Ｆ＿２加Ｏ＿２混合气体，在普通的平板型反应离子刻蚀机上，进行了深刻蚀硅的研究。当掩膜厚度约１２０ｎｍ－１５０ｎｍ的Ｃｒ薄膜时，研究了Ｏ＿２在混合气体中的比例对刻蚀形貌和刻蚀速率的影响。用获得的各向异性刻蚀工艺，己刻蚀出高度为１０μｍ的硅台阶，台阶倾角小于５°，横向腐蚀约为０．５μｍ，刻蚀表面粗糙度约１０％。     

铁电PbZr_(0.53)Ti_(0.47)O_3薄膜的磁增强反应离子刻蚀

采用磁增强反应离子刻蚀（ＭＥＲＩＥ）工艺获得了铁电ＰｂＺｒ０５３Ｔｉ０４７Ｏ３（ＰＺＴ）薄膜的微细图形．研究了用ＣＨＦ３气体在不同射频功率和气体流量下ＰＺＴ薄膜、Ｐｔ和ＡＺ１４５０Ｊ光刻胶的刻蚀速率以及刻蚀选择性的实验规律．原子力显微镜（ＡＦＭ）结果表明,获得的ＰＺＴ薄膜图形具有较高的各向异性．化学分析电子能谱（ＥＳＣＡ）结果表明,在ＣＨＦ３等离子体中Ｐｔ表面形成了一层碳氟聚合物薄膜,它对Ｐｔ的刻蚀起到钝化和保护的作用,并且最后可以在３００℃热处理３０ｍｉｎ被消除．     

Characteristics of surface and interface for ITO/PTCDA/p-Si thin film device

Recently,organic semiconductor thin fil ms becomemore and morei mportant in the application of electron-ics and photoelectronics because of their unique electron-ic and optical properties[1-4].One of main advantages oforganic thinfil ms as electronic mate…     

ITO/PTCDA/p-Si薄膜器件的表面和界面特性研究

界面态对于薄膜器件的性能具有非常重要的影响。有米用真空蒸发和溅射沉积的方法制备了ITO／PTCDA／p—Si薄膜器件,并采用X射线光电子能谱（xPs）和Ar^＋溅射技术对其表面和界面电子态进行了研究。结果表明,在ITO／PTCDA／pSi薄膜器件的界面,不仅ITO与PTCDA薄膜之间存在扩散,PTCDA与Si衬底材料之间也存在扩散现象。此外,每种原子的XPS谱表现出一定的化学位移,并以Cls和Ols谱的化学位移最为显著。     

Reactive Ion Etching of ITO Transparent Electrode of TFT—AMLCD in Ar／CF4 Plasma

Ｔhe pattern of ITO transparent electrode of pixel cells in TFTAMLCD is a critical step in the manufacturing process of flat panel display devices,the development of suitable plasma reactive ion etching is necessary to achieve high resolution display.In this work we investigated the Ar/CF4 plasma etching of ITO as function of different parameters.We demonstrated the ability of this plasma to etch ITO and achieved an etching rate of about 3.73nm/min,which is expected to increase for long pumping down period,and also through addition of hydrogen in the plasma.Furthermore we described the ITO etching mechanism in Ar/CF4 plasma.The investigation of selectivity showed to be very low over silicon nitride and silicon dioxide but very high over aluminum.     

ICP dry etching ITO to improve the performance of GaN-based LEDs

In order to improve the light efficiency of the conventional GaN-based light-emitting diodes(LEDs), the indium tin oxide(ITO) film is introduced as the current spreading layer and the light anti-reflecting layer on the p-GaN surface.There is a big problem with the ITO thin film’s corrosion during the electrode preparation.In this paper,at least,the edge of the ITO film was lateral corroded 3.5μm width,i.e.6.43%—1/3 of ITO film’s area. An optimized simple process,i.e.inductively couple plasma(ICP),was introduced to solve this problem.The ICP process not only prevented the ITO film from lateral corrosion,but also improved the LED’s light intensity and device performance.The edge of the ITO film by ICP dry etching is steep,and the areas of ITO film are whole. Compared with the chip by wet etching,the areas of light emission increase by 6.43%at least and the chip’s lop values increase by 45.9%at most.     

Precise thin-film etching process using a rectangle cathode tool

The low yield of indium-tin-oxide (ITO) usually persists throughout the processes of semiconductor production. By establishing a recycle process for ultra-precise etching of the ITO thin-film, the semiconductor industry can effectively recycle defective products, thereby reducing both production costs and pollution. This study presents a new nanotechnology application of recycle process of ITO etching using a rectangle cathode tool that offers a fast etching rate from color filter surface of TFT-LCD. In the current experiment, the design features of the etching process for a thin-film nanostructure of ITO are of major interest. Low thickness of the rectangle cathode, adequate gap-width between the cathode and the workpiece, large flow rate of the electrolyte, or high working temperature corresponds to high etching rate for ITO thin-film. An effective rectangle cathode tool and low-cost recycle processes using the electrochemical etching need little time to enable easy and clean ITO thin-film nanostructure etching.     

A planarized SiO2interlayer dielectric with bias-CVD

A Bias-CVD^TMprocess has been developed for depositing planarized silicon dioxide films. The process uses, in addition to PECVD deposition, an argon ion etch for planarization. A distinguishing feature of this process is the use of a unique sequence of depositions and etching to control contour and topography, eliminate keyholing, and reduce pinhole density. By varying this Sequence, the film topography can range from conformal to fully planarized. A cold-wall low-pressure CVD system with an eight-wafer batch and 13.56-MHz RF capability was used in this study. Because of the chamber geometry, a dc bias is induced in the wafer support during the RF plasma processing. This bias, typically a few hundred volts, provides the accelerating field for the ion etching of the film. It is the anisotropy of this etch that makes planarization possible. The film has the density and index of refraction of thermally grown oxide. The Si to O ratio is 1 to 1.9 with 8-percent nitrogen and 0.1-percent argon, by RBS. SIMS analysis shows no trace of heavy metals. The effect of process parameters has been characterized. Dynamic RAM's deposited with the sloped film show normal yield and electrical properties; there is no evidence of radiation damage.     

Ni纳米粒子掩膜用于提高GaN基LED出光率的研究

以无水乙醇为溶剂、柠檬酸为分散剂,用超声分散技术配制Ni纳米粒子分散液;将分散液用旋涂的方法在GaN基发光二极管(LED)的ITO电流扩展层上制备单层Ni纳米粒子掩膜,采用ICP(inductively coupledplasma)干法刻蚀技术在ITO层上制作出表面粗化的结构。在20 mA工作电流下,与普通GaN基LED相比,这种ITO表面粗化的GaN基LED芯片发光强度提高了30%,并且对器件的电性能影响很小。结果表明,该表面粗化技术是一种工艺简单、成本低和能有效提高LED发光效率的方法。     

聚苯乙烯球掩膜干法粗化提高LED发光效率

采用聚苯乙烯球作为掩膜层,对ITO(氧化铟锡)薄膜进行干法蚀刻实现ITO表面的粗化,提高GaN基大功率LED芯片外量子效率。利用AFM及SEM对ITO表面进行表征,比较了微球尺寸对ITO表面形貌及芯片光电参数的影响。结果表明,ITO表面经过350nm聚苯乙烯球图形化后,在未影响芯片正向电压和波长的前提下所制备的1mm×1mm波长为457nm的大功率LED芯片,亮度增加可达30%以上。     

具有纳米凹坑氧化铟锡的LED光提取效率的提高

由于低的光提取效率,氮化镓基发光二极管的应用受到了限制。氧化铟锡—氮化镓界面的光的全反射作用是造成低的光提取效率的重要原因。人们提供了多种方法来提高光提取效率。本文揭示了一种简单并且经济的方法。通过自组装和干法刻蚀的方法制作粗化的氧化铟锡薄膜。运用原子力显微镜（AFM）对表面形态和粗糙程度进行观察。测量各个样品的I-V特性、出光功率和出光辐射图并进行对比。刻蚀之后,在ITO表面形成了圆柱体和凹坑结构,它们的高度随着刻蚀时间增大。结果显示,LED的出光功率和随着刻蚀时间的增加而增加。由于圆柱体和凹坑结构的形成以及它们深度的增加,ITO-GaN界面的光的全反射减少了。因此,出光率提高。     

BST薄膜的反应离子刻蚀研究

钙钛矿结构的钛酸锶钡(BST)薄膜作为优良的介电、铁电材料在新一代的微机械系统(MEMS)、动态存储器(DRAM)及其他器件上的广泛应用,使得BST薄膜的刻蚀特性越来越重要。该文利用反应离子刻蚀装置,研究了溶胶-凝胶工艺制备的钛酸锶钡薄膜在CHF3/Ar等离子气体中的刻蚀情况。通过分析刻蚀速率及薄膜刻蚀前后表面形貌的变化,结果表明,刻蚀过程是离子轰击、离子辅助化学反应和化学反应刻蚀共同作用的结果。刻蚀速率为5.1 nm/min。Sr元素较难去除,成为阻碍刻蚀的重要因素。