单片直接数字频率合成器产品发展综述

综合论述了单片直接数字频率合成器(DDS)产品的现状、应用范围以及发展趋势。以目前国际上单片DDS产品公开发布的产品介绍资料为基础,根据DDS产品的性能和功能进行统计和分析,得到关于DDS产品的一些有用的结论。以DDS的不同功能特点为依据,分别介绍了其在不同领域的应用情况,最后给出单片DDS产品的发展趋势预测。     

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

The rapid adoption of FPGA-based systems in space and avionics demands dependability rules from the design to the layout phases to protect against radiation effects. Triple Modular Redundancy is a widely used fault tolerance methodology to protect circuits against radiation-induced Single Event Upsets implemented on SRAM-based FPGAs. The accumulation of SEUs in the configuration memory can cause the TMR replicas to fail, requiring a periodic write-back of the configuration bit-stream. The associated system downtime due to scrubbing and the probability of simultaneous failures of two TMR domains are increasing with growing device densities. We propose a methodology to reduce the recovery time of TMR circuits with increased resilience to Cross-Domain Errors. Our methodology consists of an automated tool-flow for fine-grain error detection, error flags convergence and non-overlapping domain placement. The fine-grain error detection logic identifies the faulty domain using gate-level functions while the error flag convergence logic reduces the overwhelming number of flag signals. The non-overlapping placement enables selective domain reconfiguration and greatly reduces the number of Cross-Domain Errors. Our results demonstrate an evident reduction of the recovery time due to fast error detection time and selective partial reconfiguration of faulty domains. Moreover, the methodology drastically reduces Cross-Domain Errors in Look-Up Tables and routing resources. The improvements in recovery time and fault tolerance are achieved at an area overhead of a single LUT per majority voter in TMR circuits.     

Thermal Monitoring of Self-Checking Systems

With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with questions of on-line temperature monitoring in safety-critical systems. First the possible temperature sensors are reviewed and basic principles of self-checking systems including such sensors are detailed, then a new temperature sensor cell with extremely good parameters designed especially for DfTT applications is presented. The basic questions of integrating thermal sensors into self-checking systems are also discussed.     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

I-V characteristics and reliability parameters for the set of hardened SOI MOSFET's with special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300 °C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current rise; for tungsten metallization (contacts, conductor lines and vias) I-T and R-T characteristics, failure time. The SOI MOSFET standard compact SPICE model BSIMSOI with traditional temperature limit of 150 °C is modified to be used for CMOS IC simulation in the extended temperature range up to 300 °C. The results indicate that the 0.5–0.18 μm SOI MOSFET's with tungsten metallization have stable electrical behavior that makes them possible to be used during implementation of HT CMOS IC's (to 300 °C).     

Electrical performance increase of concentrator solar cells under Gaussian temperature profiles

Linear solar concentrators focus radiation onto the solar cell achieving a Gaussian illumination profile. Most of these concentrators use an active cooling system to evacuate the energy not converted into electricity to avoid undesirable overheating. Heat sinks can cause different temperature profiles in the cell depending on the cooling mechanism. Two temperature patterns are most common: the Gaussian and the anti‐Gaussian. The effect of these temperature curves on the cell's electrical parameters has been analysed and characterised numerically and experimentally under different concentrated radiations. A power output increase is shown when the cell is subjected to a Gaussian temperature profile. Contrarily, the cell efficiency decreases more than 3% under the anti‐Gaussian temperature profile. It is demonstrated that it is possible to tailor the temperature profile to maximise voltage output for determined illumination conditions. Copyright © 2011 John Wiley & Sons, Ltd.     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

A Novel SR Latch Device Realized by Integration of Three-Terminal Ballistic Junctions in InGaAs/InP

In this letter, a novel sequential logic device based on three-terminal ballistic junctions (TBJs) is proposed and demonstrated. Two TBJs and two in-plane gates are laterally integrated in a high-electron-mobility InGaAs/InP quantum-well material by a single-step lithography process. Electrical measurements reveal that the integrated device functions as a set-reset (SR) latch with voltage gains at room temperature. The demonstrated device provides a new and simple circuit design for SR latches in digital electronics.     

Applications of passive integration

Applications of the passive integration technology are described. A broad range of specific application examples are chosen with the aim of illustrating the possibilities for functional integration within this technology. The discussion is technical rather than commercial, to underline the advantages as well as the limitations of a passive integration approach. This paper is directly complementary to those on the technology of passive integration and on electromagnetic simulations of passive IC's in this edition.     

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100°C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100°C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs     

Theoretical basis for controlling minimal tumor temperature duringinterstitial conductive heat therapy

This paper describes simulation of steady-state intratumoral temperatures achieved by a simple modality of local heat therapy: interstitial treatment with parallel arrays of warmed, conductive heating elements. During "conductive heating" power is directly deposited only in the interstitial probes. Adjacent tissue is warmed by heat conduction. Simulations of interstitial conductive heating involved solution of the bioheat transfer equation on a digital computer using a finite difference model of the treated tissue. The simulations suggest that when the complete temperature distributions for conductive interstitial hyperthermia are examined in detail, substantial uniformity of the temperature distributions is evident. Except for a thin sleeve of tissue surrounding each heating element, a broad, flat central valley of temperature elevation is achieved, with a well defined minimum temperature, very close to modal and median tissue temperatures. Because probes are inserted directly in tumor tissue, the thin sleeve of overheated tissue would not be expected to cause normal tissue complications. The temperature of the heated probes must be continuously controlled and increased in the face of increased blood flow in order to maintain minimum tumor temperature. However, correction for changes in blood flow is possible by adjusting probe temperature according to a feedback control scheme, in which power dissipation from each probe is the sensed input variable. Conductive interstitial heating with continually controlled probe temperature deserves investigation as a technique for local hyperthermia therapy.     

Cool Chips: Opportunities and Implications for Power and Thermal Management

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.     

The radiation test based assessment of process quality and reliability for conventional 65-nm CMOS technology

This work presents a solution for radiation hardness assessment using compact and productive X-ray facilities, as well as the automated measurement system. The radiation test procedure can be integrated in commercial IC's process as a mandatory option for providing high reliability and radiation hardened IC projects.Using the radiation test procedure as a one of technology stage, the assessment of total ionizing dose (TID) hardness was done for test structures, which were fabricated in conventional 65 nm CMOS technology.     

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

A wired-AND current-mode logic (WCML) circuit techniquein CMOS technology for low-voltage and high-speed VLSI circuitsis proposed, and a WCML cell library is developed using standard0.8 micron CMOS process. The proposed WCML technique appliesthe analog circuit design methodologies to the digital circuitdesign. The input and output logic signals are represented bycurrent quantities. The supply current of the logic circuitis adjustable for the required logic speed and the switchingnoise level. The noise is reduced on the power supply lines andin the substrate by the current-steering technique and by thesmooth swing of the reduced node potentials. Precise analogcircuits and fast digital circuits can be integrated on the samesilicon substrate by using the low noise property of the WCML.It is shown by the simulations that at low supply voltages, theWCML is faster and generates less switching noise when comparedto the static-CMOS logic. At high speeds, the power dissipationof the WCML is less than that of the static-CMOS logic.     

A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V _DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.     

Optical interaction in active analog circuit elements

This publication introduces (spectral) photon emission (PEM) and electro-optical frequency mapping (EOFM/LVI) measurements to analog circuit elements (simple, cascode and low-voltage current mirrors). Different operating conditions of the devices are probed and the voltage dependence of the signals is analyzed. Results partly show close similarities to optical probing of digital IC's, but also differences in voltage dependence and signal levels due to more complicated voltage and signal distributions along the devices.     

A wafer-level approach to device lifetesting

An innovative wafer-level methodology is introduced and used to determine the thermal activation energies of TriQuint semiconductor’s TQPED devices. Activation energies of 2.77 eV and 2.44 eV are calculated for the depletion-mode and enhancement-mode devices, respectively. This accelerated lifetest technique utilizes a special reliability test structure that includes an on-wafer heating element around the device under test (DUT). The heating element easily achieved temperature above 275 °C without the need to bias the device. This allows the exclusive study of thermally activated failure mechanisms. The special reliability test structure allows the stressing of individual devices at different temperatures on the same wafer. This built-in flexibility allows for a fast and efficient means of evaluating device reliability by eliminating packaging overhead and considerations. In wafer form it becomes possible to spatially map the reliability of devices under test. It is also easier to observe the physical degradation of devices and determine the failure mechanisms.     

Real-time furnace modeling and diagnostics

Precise control of process temperature has become increasingly important in today's semiconductor industry. Multizone batch furnaces are used widely in current manufacturing lines, and high reliability of furnace systems is a crucial factor in achieving high product yield. However, uncertainty caused by sensor noise and failure may degrade reliability. In this work, the authors develop a methodology based on thermal modeling and sensor fusion techniques to detect temperature sensor failures, power supply failures, and system faults for the multizone furnace systems. The typical types of failures have been defined. The impact of single failures and different combinations of failures on the system behavior has been studied. The furnace system has been modeled based on both physical considerations and experimental data extraction. The fault detection methodology has been tested in simulations. Principal component analysis is utilized for choosing data types for different fault detection purposes. Sensor fusion is used to enhance reliability. Simulation results show that all different types of failures can be detected when data are rich enough. Experimental results show that all single failures and some of the failure combinations can be estimated when only steady-state and cooling-down data are utilized.     

An integrated approach for hierarchical verification of VLSI mask artwork

An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design methodology allows SLAVE to use the separate hierarchical representations in the logic, circuit, and layout models to completely verify the connectivity of the mask layout. SLAVE has been successfully adapted to both bipolar and CMOS technologies; it provides error detection down to specific signal nets and device nodes and is extremely fast. SLAVE typically runs under 70 min on a VAX 11/780 for a complex IC containing up to 50K discrete devices and is modeled using six levels of hierarchical nesting.     

可编程光纤传输实验系统的设计

设计了一套以光收发模块为核心的数字信号光纤传输实验系统.数字信号处理部分选用了复杂可编程逻辑器件EPM7128SLC84-15,通过拨码开关可以产生伪随机序列并作为输入信号进入EPM7128输入端,对其进行任意编码后,信号进入光纤传输.接收端再进行解码处理,并用LED或示波器显示结果.实验系统工作可靠稳定,其不仅可用于数字信号光纤传输实验教学,而且在较短距离、较大容量的局域网信号传输中具有实用价值.