介质隔离技术的新进展

本文介绍一种成品率高，而实现全介质隔离的ＳＯＩ技术。该技术利用助粘层对硅片进行粘合，实现以单晶硅取代ＳｉＯ２一多晶硅介质隔离片中的多晶硅支撑体，避免了长时间高温淀积多晶硅过程，从而克服了随硅片直径增加而加剧的硅片翘曲形变，简化了操作，缩短了工艺流程，便于批量加工，适用于大直径硅片，其成品率亦比ＳｉＯ２－多晶硅介质隔离高出５０％，并在双极型模拟电路抗辐照加固的实际试用中取得了成品率高、电参数一致性好     

SiGe与SOI：模拟／混合信号电路的先导技术

ＳｉＧｅ与ＳＯＩ：模拟／混合信号电路的先导技术亦然摘编在当今众多模拟／混合信号工艺技术中，又出现两种新兴技术。这就是正在崭露头角的硅－锗异质结双极晶体管（ＳｉＧｅＨＢＴ）工艺和已经在大多数先进的互补双极（ＣＢ）工艺中大显身手的绝缘体上硅（ＳＯＩ）技术...     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

200V／μs高速宽带运算放大器的设计考虑

介绍了一种采用介质隔离互补双极工艺制造的单片高速宽带电压反馈型运算放大器。着重分析了电路的工作原理，设计特点和制造工艺。最后，用ＰＳＰＩＣＥ模拟程序和实验结果证明了该设计的正确性。     

集成电路隔离技术概述（续Ⅰ）

集成电路隔离技术概述（续Ⅰ）宋湘云编译６　全凹槽氧化物ＬＯＣＯＳ工艺全凹槽氧化物ＬＯＣＯＳ工艺已经在双极ＩＣ制造中得到广泛应用。在生长衬垫氧化物和淀积Ｓｉ＿３Ｎ＿４后，腐蚀掉标准埋层集电极双极工艺中二分之一到三分之二的外延层，光刻后留下的Ｓｉ＿３Ｎ＿...     

薄膜全耗尽SOI门阵列电路设计与实现

在Ｄａｉｓｙ系统上设计出通用性强、使用方便的ＳＯＩ门阵列母版及门阵列电路，并采用１．５ｕｍＣＭＯＳ／ＳＯＩ工艺在薄膜全耗尽ＳＩＭＯＸ材料上得以实现，其中包括多种分频器电路和环形振荡器，环振可工作在２．５Ｖ，门延误时间在５Ｖ时为４３０ｐｓ。     

薄膜全耗尽CMOS／SOI—下一代超高速Si IC主流工艺

本文较为详细地分析了薄膜全耗尽ＣＭＯＳ／ＳＯＩ技术的优势和国内外ＴＦ ＣＭＯＳ／ＳＯＩ器件和电路的发展状况，讨论了ＳＯＩ技术今后发展的方向，得出了全耗尽ＣＭＯＳ／ＳＯＩ成为下一代超高速硅集成电路主流工艺的结论。     

S1240专用MBLIC LSI

本文叙述了Ｓ１２４０数字程近电话交换机专用的一种用户接口电路的结构与功能。采用以双极工艺为基础的ＢｉＣＭＯＳ制造技术，使用相同的结深度，实现了高，低压双极型管与ＣＭＯＳ管的结合，制造出ＭＢＬＩＣ ＬＳＩ，并通过比利时贝尔电话公司质量认证。     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

用IGBT设计特种电源

绝缘栅双极晶体管（ＩＧＢＴ）开关电源,特别是特种电源,像大功率开关电源、ＵＰＳ电源、变频电源及变频调速装置等的功率变换器,其核心的功率器件通常为双极型功率晶体管和ＭＯＳＦＥＴ（金属氧化物半导体场效应晶体管）。但是随着对小型、轻量、高频、高效和低噪音的...     

Self-aligned complementary bipolar technology for low-powerdissipation and ultra-high-speed LSIs

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit     

Process and device optimization of an analog complementary bipolarIC technology with 5.5-GHz fT pnp transistors

An analog complementary bipolar IC process has been developed featuring 9.0-GHz f_T npn and 5.5-GHz f_T pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the H_FE×V_A of pnp transistors is 350 V with f_T of 5.5 GHz and f_max of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz f_T npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET's and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability     

一种PN结隔离互补双极工艺

介绍了几种互补双极工艺的结构和特点，详细阐述了一种基于N型外延的PN结隔离互补双极工艺；着重探讨了隔离制作技术和PNP管设计要点，并对实际流片结果进行了讨论。     

Negative impedance converter with a translinear implementation

A new negative impedance converter circuit, which is a current inversion type (I-NIC), is described. The basic cell consists of a mixed translinear loop comprising two pnp and two npn bipolar transistors. This cell is used in conjunction with a constant current source and two complementary current mirrors. The characteristics and the properties of the practical realization are presented and discussed. A new bandpass filter, which is a current processing circuit, using the I-NIC and a current-controlled current source (CCCS) are also introduced. Experimental results are given.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I–V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I²L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.     

High-speed low-power direct-coupled complementary push-pull ECLcircuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

一种新型的双极功率器件—BST

针对常规双极功率晶体管（ＢＰＴ）中存在的高频、高电流增益和高ＣＥ击穿电压间的固有矛盾，基于一新工艺提出了一种新型的双极功率器件──ＢＳＴ（ＢａｓｅＳｈｉｅｌｄｉｎｇＴｒａｎｓｉｓｔｏｒ）结构。分析了ＢＳＴ夹断后的两维电场解析解，可知深Ｐ＋多晶硅基区的引入对有源Ｐ基区产生明显的电场屏蔽效应，该基区屏蔽效应随Ｐ＋基区深入Ｎ－区中的深度Ｌ的增加以及相邻Ｐ＋基区间距２Ｄ的减小而增强。正是这种基区屏蔽效应，使得ＢＳＴ的特征频率ｆＴ、电流增益ｈｆｅ和ＣＥ击穿电压ＢＶｃｅ０都较常规ＢＰＴ大为提高，较好地解决了常规ＢＰＴ中存在的主要矛盾。实验验证了理论分析的结果。