高性能硅基MOS电光相位调制器

提出了一种SOI新型MOS电容型电光调制器.与普通单一电容型MOS调制器相比,由三层栅氧化层形成的新型MOS电容型调制器提高了调制效率.模拟显示,调制电压和调制长度乘积为VπLπ=2.4V·cm,上升和下降时间分别为80和40ps,带宽达到了8GHz.通过减小器件尺寸能进一步提高调制效率和调制速度.     

一种具有低RC时间常数的新型电吸收调制器的研制

我们研制了一种带有插入电荷层和倒台型脊波导结构的新型集总型电吸收调制器（DU-EAM)。同时,为了验证这种新型器件具有低的RC时间数,我们也制备了另外两种具有直脊波导的集总型电吸收调制器作为实验参照组,其中一个含有电荷层,另一个不含电荷层。三种器件的测试结果表明,被插入一层电荷层的两种器件（D-EAM和DU-EAM）的电容明显小于普通的电吸收调制器。-3v偏压下,三种器件—N-EAM, D-EAM, DU-EAM 的电容分别为0.375PF, 0.225PF and 0.325PF,最佳偏置电压-3v下对应的最高调制带宽可以达到28.3GHz。DU-EAM因为具有较宽的有源区宽度,其-3V下的调制消光比高达25dB,-1v至-2v间调制效率高达13dB/v。     

一种n+/p+环接MOS电容的研制

电容是集成电路的一个组成部分,由于MOS电容与CMOS工艺流程匹配,所以应用广泛.为了改善传统MOS电容值随电压特性的改变而变化的现象,并提高MOS电容值的稳定性,提出了一种新型MOS电容的制作方法和连接结构.新结构是将传统MOS电容的一个n+电极更改为p+电极,这样可以使器件的输入电势极性更改前后都为栅氧电容,但在极性更替间,由于有耗尽层存在,电容仍会变小.将两个新结构MOS电容环接,即将其中一个电容的多晶硅层与另一个电容的阱相连接,并用金属连线引出电极,测试结果表明,与传统MOS电容相比,新型MOS电容提升了零电压附近突变区域电容最低值,减小了器件电流波动幅度,有利于提高器件的可靠性.     

高速集总型双耗尽电吸收调制器的研制

设计并研制了一种新的直脊波导集总型电吸收调制器——集总型双耗尽电吸收调制器（D-EAM）。同时,作为实验对照组,还制备了一种普通有源区结构的电吸收调制器（N—EAM）。两种器件的测试结果对比分析表明,D-EAM的电容明显要小于N—EAM。脊波导长度为250μm,宽度为2．5弘m的D-EAM在－3V偏压下电容为0．225pF,对应的调制带宽估算为28．3GHZ;1550nm输入波长条件下,D-EAM在偏压为－1V至－2V之间调制效率最大,达到10dB／V,而－3V、－6V下的调制深度分别为22dB和26dB,满足40Gbit／s光纤通信要求。     

SOI光波导高速电光调制器的研究进展

介绍了不同截面大小的SOI(silicon-on-insulator)波导单模条件,详细描述了几种降低传输损耗,消除偏振相关,提高耦合效率的技术手段.分析比较了一种带有MOS(metal-oxide-semiconductor)电容结构和一种具有微环结构的高速电光调制器,其调制频率分别达到10和1.5GHz.     

SOI光波导高速电光调制器的研究进展

介绍了不同截面大小的SOI(silicon-on-insulator)波导单模条件,详细描述了几种降低传输损耗,消除偏振相关,提高耦合效率的技术手段.分析比较了一种带有MOS(metal-oxide-semiconductor)电容结构和一种具有微环结构的高速电光调制器,其调制频率分别达到10和1.5GHz.     

基于低压CMOS工艺的新型负电压型电荷泵电路

采用UMC 0.18 μm 1.8 V/3.3 V CMOS工艺设计并流片验证了一个应用于生医刺激器的新型负电压型电荷泵电路.介绍了几种典型的负电压型电荷泵电路,比较其优缺点,在此基础上设计了一个新型4级交叉耦合型负电压电荷泵.和现有的结构相比,该电路在启动过程和工作过程中都不存在过压问题,器件任意两端口之间的电压均小于电源电压VDD,同时降低了MOS器件衬底效应、反向漏电流对电荷泵效率的影响.电荷泵的电容采用MIM电容,升压电容为50 pF,输出电容为100 pF.芯片面积为2.3 mm×1.3 mm,测试结果表明负电压型电荷泵电路输出电压为-10.3 V,系统最高效率为56％.当输出电流为3.5 mA时,输出电容为100 pF时,纹波电压为150 mV.     

电阻耦合型神经MOS晶体管及其差分四象限模拟乘法器

电阻耦合型神经 MOS晶体管是在电容耦合 (浮栅 )型神经 MOS晶体管基础上提出来的 ,它克服了电容耦合型神经 MOS晶体管中由于电容耦合而产生的缺点。文中介绍了电阻耦合型神经 MOS晶体管的基本结构和特点 ,并将它应用于差分四象限模拟乘法器     

聚合物共面波导行波电极电光调制器

用聚合物材料BPAN-NT设计并初步成功制作了共面波导(CPW)行波电极电光调制器。用反应离子刻蚀(RIE)的方法制作脊波导,通过电晕极化使芯层有电光效应,利用电镀方法制作厚行波电极。对调制器的各项特性参数进行了测试,测得调制器的微波损耗系数0α=0.9 dB/cm.(GHz)1/2、在1.317μm波长上Vπ=250 V,由此算得芯层材料的电光系数3γ3=3.7 pm/V,同时测得消光比为13.49dB、插入损耗为18.6 dB,在8 GHz的微波频率上观察到了调制光信号,理论计算3 dB光调制带宽为43.77 GHz。     

全光纤聚合物电光调制器

设计了一种新型的基于长周期光纤光栅的全光纤聚合物高速电光调制器。应用多层光波导和耦合模理论,分析了这种调制器中长周期光栅的谐振波长随施加在聚合物上调制电压的变化。得出在电压仅为8V时对长周期光栅谐振波长的调制就可达到20nm。     

一种应用于48V-1V系统的隔离型混合模式降压变换器

提出了一种应用于48 V-1 V系统的隔离型混合模式降压变换器,利用飞电容和变压器实现高转换比应用下的高转换效率。混合变换器结合了开关电容变换器和开关电感变换器,其中飞电容承担了部分电压降,实现了功率开关管电压应力的降低。由于开关节点处的电压摆幅较小,开关损耗随之减小;通过使用更低压的功率开关管,实现功率开关管导通损耗减小。在此基础上,隔离型混合模式降压变换器通过时序控制可以实现软开关,进而实现功率开关管开关损耗减小,使得整体效率提升。在隔离型混合模式降压变换器中,飞电容还具有隔直电容的作用,可以防止变压器偏磁。在典型应用下,即在48 V输入电压、1 V输出电压、500 kHz开关频率下,峰值效率为94.84%。     

基于高压BCD工艺的内集成自举电路

设计了一款基于高压BCD工艺的内集成MOS自举电路,将其应用于高压集成电路(HVIC)。对传统的内集成MOS自举电路进行改进,该改进版内置MOS自举电路集成升压控制模块,实现在HVIC通电后屏蔽HVIC输入信号,并通过集成的升压电路将自举电容电压充到预期值,解决了以往使用传统的内置MOS自举功能时,因充电速度慢、充电电压低所导致的触发HVIC欠压保护和电器频繁停机问题。基于SMIC 3μm BCD工艺对所设计的自举电路的HVIC进行流片验证。测试结果表明,升压电路将HVIC供电电压从15 V升高至16.4 V,自举电容电压可达到预期值,同时实现了替代外接自举二极管或通过SOI工艺内置自举二极管的自举功能。     

Area-efficient linear regulator with ultra-fast load regulation

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.     

Compensation of bipolar monolithic circuits using the parasitic capacitance of diffused resistors

A method of compensating bipolar integrated circuits which uses the parasitic capacitance of diffused resistors is studied. The advantages over other methods are: compatibility with the standard bipolar fabrication process, ease of implementation, and the possibility of controlling the overall bandwidth of an amplifier through adjustment of the bias of a resistor (for variable bandwidth applications or for compensation of process variations). The main drawback is the large size required. The sensitivity to process-parameter variations of the resulting compensation is shown to be comparable to that achieved with a MOS or N/SUP +/P capacitor. The MOS compensation is more stable with temperature variations. The diffused resistor models are shown to yield accurate results as long as a sufficient number of lumped sections are used when large area resistors are considered.     

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250 mV start-up voltage

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm² and can deliver 10.3 μW at 3 V to an external battery or capacitor.     

Improved ESD properties by combining GaN-based light-emitting diode with MOS capacitor

An InGaN/GaN light-emitting diode (LED) combined with a metal–oxide semiconductor (MOS) capacitor has been fabricated for high electrostatic discharge (ESD) protection. By connecting a MOS capacitor in parallel with the GaN-based LED, a level of defense against the ESD is significantly strengthened from 200 to 1900 V of human body mode (HBM), which corresponds to 6- to 7-fold enhancement in the ESD robustness of LEDs.     

Technique for monitoring slow interface trap characteristics in MOScapacitors

A new experimental technique presented in the Letter simultaneously extracts the trap response time as well as trap density and energy in the silicon bandgap. The technique is illustrated by measuring the trap density increase in a MOS capacitor due to constant current stressing and is compared with the results obtained using the conventional quasistatic C/V technique     

6H－SiC MOS结构电特性及其辐照效应的研究

对SiC MOS结构辐照引起的电参数退化及其电特性进行了研究。结果说明:在氧化层电场较高时Fowler-Nordheim隧穿电流决定着SiC MOS结构的漏电流,当幅照栅偏压为高的正电压时,电离幅照对SiC MOS电容的影响会更明显,SiC MOS器件比Si器件具有好的抗辐照的能力,在58kGy(Si)的辐照剂量下,其平带电压漂移不超过2V。     

New dynamic RAM Cell for VLSI memories

A novel high-alpha-particle-immunity and high-density dynamic RAM cell with readout signal gain is proposed. The cell is composed of a MOSFET for charge transfer, a MOS capacitor for charge storage and a junction FET (JFET) with buried channel under the MOS capacitor. The buried channel is dynamically switched according to whether there is charge-storage or not. The cell has extremely small collection efficiency for charges generated by alpha-particles, and allows a large amount of leakage charges due to its peculiar structure. Thus, it can achieve high packing density.     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.