基于微波光子的一体化可重构电子系统

针对一体化电子系统必须具备宽带、多频段信号处理能力等要求，提出了一种基于微波光子技术的一体化可重构电子系统方案，采用微波光子混频技术实现宽带、多频段射频信号光域变频，使用微波光子交换技术实现信道复用，系统具备四路并行处理能力，通过软件配置可动态重构各信道功能。     

无人机综合一体化测控终端设计

现有无人机(UAV)测控终端设备综合化程度不高,互通能力较差,不能满足未来无人机的模块化、综合化、通用化发展趋势。针对上述问题,采用“系统高度集成+功能综合可重构”的模式,提出一种可适用于机载,也可适用于地面的无人机综合一体化测控终端设计。采用标准模块构建开放式硬件平台,实现高集成综合处理能力;设计了动态重构的通信波形加载机制,完成通用测控链路中通信体制的在线更新及升级;进行标准化通信协议研究,提供不同型号测控链路的互联互通基础。实测结果表明,该设计可在数分钟内完成动态重构并有效支撑不同任务。     

一种通用飞机综合电子系统架构研究

随着我国国民经济的快速发展和低空领域逐步开放,限制通用航空市场发展的主要政策障碍得到解除,我国通用航空迎来了新的发展机遇。文章依据通用飞机综合电子系统功能需求,提出了一种通用飞机一体化综合电子系统的总体架构,突破了安全性设计技术、多系统综合技术等关键技术,并将系统重构的设计融入了整个综合电子系统的设计,具有广泛的应用前景。     

天基ISAR电子系统论证与设计

为了天基逆合成孔径雷达（ISAR）成像的理论技术向可实现性方向发展的需要,提出了以一体化综合电子系统和可重构计算机为核心技术的天基ISAR硬件电子系统设计方案。此方案结合了国外先进航天电子系统的设计,将基于1553B的总线结构和模块化设计思想贯穿于整个系统中,并对系统合理性进行了说明和论证。这种一体化的结构可以有效地简化设计、提高抗辐射性能、节约能量、减少体积和质量,并能解决设备之间的快速对接、故障设备快速更换的问题。     

调频斜率失配干扰与通信一体化研究

干扰通信一体化设备整合了电子干扰和通信功能，能显著提高作战效能，是综合一体化电子系统的一个重要研究方向。针对单线性调频（LFM）信号携带通信数据导致通信速率较低的问题，提出一种基于调频斜率失配干扰的干扰通信一体化信号设计方法，该一体化信号由多种同调频斜率不同载频的LFM信号组成，LFM信号的调频斜率和载频由通信信息从相应序列映射决定，脉间LFM信号的特征参数由于通信信息的不同表现出随机性，可在不影响雷达干扰效果的前提下，实现通信速率的提升。在通信接收端，通过去斜处理和快速傅里叶变换（FFT）判断每个频点是否过门限，解析过门限的频点得到通信信息。仿真结果表明，该信号能够产生压制式干扰效果和进行高速率通信数据传输。     

一种双波段可重构功率放大器仿真设计

可重构输入匹配采用一种基于L型的电路结构,通过一个单刀单掷开关电路使该结构接入一段微带线,实现不同工作频率下输入阻抗的自动补偿。输出匹配实现并发双频段工作,在早期三段式微带线的基础上重新进行公式推导,提出了更易实现的四段微带线串联结构。该功率放大器采用了可重构结构与并发双波段匹配网络结合的方式,因此只采用了一个开关。电路结构简单,且开关切换时对电路性能影响较小。仿真结果表明,该功率放大器的匹配状态和性能良好,为现有的可重构功率放大器设计提供了一种思路。     

基于动态可重构的FFT处理器的设计与实现

提出了一种基于局部动态可重构(DPR)的新型可重构FFT处理器.相比传统的FFT设计,该设计方法在重构时间上得到了很大改进,同时,处理器能够动态地添加或移除重构单元.采用新颖的FFT控制算法,使得可重构部分面积很小.该处理器结构在Xilinx Viirtex2p系列FPGA上进行了综合及后仿真.较之Xilinx IPcore,其运算效率明显提高,而且还实现了IP核所不具备的动态可重构性.     

雷达与通信信号一体化侦察系统半实物仿真

阐述了雷达与通信信号情报侦察一体化系统的组成及结构,建立了一体化电子侦察半实物仿真系统。系统仿真试验验证了雷达与通信信号一体化电子侦察系统的信息流程,以及系统具有的资源共享、动态重构、多手段侦察信息综合应用等功能。     

DIMA系统网络通信技术方案选择

分布式综合模块化航空电子系统(DIMA)已成为未来新一代航空电子系统的发展方向。为解决DIMA系统网络通信技术方案的选择问题,构建了系统体系结构模型,以通信、导航与识别综合系统为切入点讨论了其与联合式系统和综合模块化航空电子系统的区别与联系;基于此,总结了DIMA系统的网络通信需求,并通过对比分析光纤通道、航空电子全双工交换式以太网和时间触发以太网,确定了采用时间触发网络实现DIMA系统网络互连在实时可靠通信和系统增量升级等方面的优势。     

园区网络下的可信网络框架设计与研究

由于当前终端接入园区网络,并在园区网络内与其他终端建立通信的模式已无法满足目前的安全要求。文中提出了基于园区网络的可信网络框架设计与研究,设计了一种园区网络的可信网络连接[1]框架的安全接入认证协议,建立可信安全通信通道的验证方法。通过安全分析表明,该方案能够确保终端自身的完整性和安全性,安全可信地接入可信网络,并在可信网络上完成与目标主机之间建立安全可信的通信通道,保证整个园区网络办公环境的安全。     

实时时钟芯片DS1302在DSP嵌入式系统中的应用

在许多嵌入式应用场合需要实时时钟的功能,通常DSP（数字信号处理器）芯片并不具备此功能,因此在实际使用过程中需要外扩实时时钟芯片来解决该问题。文中介绍了串行时钟芯片DS1302的功能以及在DSP嵌入式实时处理系统中的应用,给出了基于CPLD（复杂可编程逻辑器件）的控制器逻辑设计和DSP底层软件驱动编写的方法,指出了逻辑设计中需要注意的问题。实现一种分层、高效和可移植的嵌入式系统。经过长期的试验．实时时钟运行稳定准确,取得了良好的效果。     

一种VxWorks环境下双冗余网卡的设计与应用

网络通信是现代通信系统领域的主要方式。网卡作为网络通信系统的关键组成部分,一旦发生故障,将导致整个网络通信系统的全部崩溃而不能工作。实现双冗余式网络构架是提高现代网络通信系统的可靠性和稳定性的一种重要方式,而双冗余网卡则是其中核心。文章简要介绍了一种双冗余网卡的实现机理、技术指标、结构特征、硬件组成以及软件描述。     

CDMA／SDMA系统性能分析

空分多址接入技术（SDMA）可以通过信号不同的空间传播路径来区分用户，从而提高了蜂窝移动通信系统容量．而此技术又可以和其他多址方式相互兼容，比如频分多址，时分多址，码分多址．CDMA／SDMA系统就是码分多址和空分多址两种接入技术相结合的系统．该系统可通过时空编码实现的．文中分析此种系统的性能，并与多用户环境下的CDMA系统进行了比较．     

Digital optical computing

This paper concerns binary digital computing systems in which the information-carrying medium consists entirely or primarily of photons. The paper begins with a review of analog, discrete, and binary methods of representing information in a computer, followed by a survey of many techniques for implementing binary combinatorial and sequential logic functions with individual optical devices and arrays of devices. Next is a discussion of communication, interconnection, and input-output problems of digital electronic and optical computers at the gate, chip, and processor level. A particular architecture for implementing general sequential optical logic systems including digital optical processors is described. This architecture avoids some of the interconnection problems of electronic integrated circuits and VLSI systems, and offers the potential of non von Neumann parallel digital processors. Finally, the current limitations and future needs of optical logic devices and digital optical computing systems are outlined.     

On‐Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.     

Serial communication circuit with optimized skew characteristics

This letter highlights features of an optimized serial communication system, including an oversampling technique of data recovery, issues related to off-board communications and a modified universal asynchronous receiver transmitter (UART) implemented in a programmable logic device (PLD). The resulting system provides high skew tolerance at 44 Mb/s data rate and has achieved a transmission distance of 130 m, at this rate, with the aid of an enhanced differential transceiver circuit. The principal application is for embedded systems with medium distance communication requirements. This UART can be integrated with other communication functions, such as packet routing switches, in a PLD device     

Secure communication with a chaotic system owning logic element

In recent years, various chaotic systems have been introduced in literature to be used in different branches of science. In the field of secure chaotic communication, more complex chaotic systems are proposed, such as high dimensional (4D, 5D), multi-scroll, surface equilibrium point, to enhance communication security level. In this study, a chaotic system owning logic element is used for increasing the level of security of chaotic communication system, which has not been previously implemented for this purpose in the literature. The used chaotic system includes signum functions, maximum function and absolute operation term. Also, there are analog devices and digital device in the electronic circuit of this chaotic system. These properties increase the complexity of the chaotic system and the security level. Sliding mode control method is preferred for the synchronization part of the secure communication. In this regard, numerical analysis and electronic circuit design of the secure chaotic communication system by using the chaotic system owning logic element have been performed successfully.     

FLC-Based MBWIMA/UMTS Protocol for Multimedia Services in UTRA TDD Mode

An intelligent medium access control (MAC) protocol based on fuzzy logic control (FLC) is proposed and compared with a general packet radio system in UMTS (GPRS/UMTS), priority scheme and the movable boundary wireless integrated multiple access in UMTS (MBWIMA/UMTS) protocols. The integrated video/voice/data services of UMTS in UTRA TDD mode have different transmission properties. By fuzzy logic control, the resources of the wireless communication can be intelligent assigned for different types of mediums. The voice-video dropping probability and data packet delay are input to FLC to optimally select the maximum number of voice/video slots. Voice activity detector (VAD) and multiple access interference in single cell are also considered in the simulations.     

A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems

In this paper, design and implementation of a baseband receiver integrated circuit (IC) for a downlink multi-carrier code-division multiple access (MC-CDMA) system are presented. This MC-CDMA system aims to provide higher data transmission capacity than the current wide-band CDMA systems in mobile cellular communication environments. The proposed chip provides a robust tracking mechanism for synchronization errors and an accurate channel estimation strategy to overcome the challenge of outdoor fast-fading channels. Besides, low-power and low-complexity architecture design techniques are adopted to satisfy mobile receiver needs. Experimental results of the designed baseband receiver integrated circuit demonstrate its superior system performance and great reduction in power consumption. The chip was fabricated in a 0.18-mum CMOS technology with a core area of 2.6 mm times 2.6 mm. It can support up to 21.7-Mbps uncoded data rate in a 5-MHz bandwidth. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1 V.     

基于5G的警务集群系统

通过分析集群通信系统沿专网与公网方向发展演进的技术趋势,结合公安调度需求研究了基于5G切片的警务集群系统体系结构,包括应用层、服务层、传输层、终端层、标准及管理体系和安全保障体系。在网络组网架构方面,通过超高可靠低时延通信(Ultra-reliable and Low Latency Communications,uRLLC)切片传输控制信号,增强型移动宽带(Enhanced Mobile Broadband,eMBB)切片传输业务内容,并提出集群业务软件中通信调度业务逻辑、综合业务适配和维护管理软件的模块组成,对其应用的协同算法、时延保证、安全可靠性和可扩展性等关键技术问题给出建议。基于多智能体控制模型提出多接入边缘计算(Multiple Access Edge Computing,MEC)服务器之间状态同步协调算法,为警务集群系统在5G技术体制下的进一步发展提供了基础。