| 基于动态可重构的FFT处理器的设计与实现 |
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| 引用本文： | 潘伟,刘欢,李广军.基于动态可重构的FFT处理器的设计与实现[J].微电子学,2009,39(1). |
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| 作者姓名： | 潘伟 刘欢 李广军 |
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| 作者单位： | 电子科技大学通信与信息工程学院,成都,610054 |
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| 摘 要： | 提出了一种基于局部动态可重构(DPR)的新型可重构FFT处理器.相比传统的FFT设计,该设计方法在重构时间上得到了很大改进,同时,处理器能够动态地添加或移除重构单元.采用新颖的FFT控制算法,使得可重构部分面积很小.该处理器结构在Xilinx Viirtex2p系列FPGA上进行了综合及后仿真.较之Xilinx IPcore,其运算效率明显提高,而且还实现了IP核所不具备的动态可重构性.
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| 关 键 词： | 动态部分可重构 FFT处理器 |
Implementation of FFT Processor Based on Dynamic Partial Reconfiguration |
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| PAN Wei,LIU Huan,LI Guangjun.Implementation of FFT Processor Based on Dynamic Partial Reconfiguration[J].Microelectronics,2009,39(1). |
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| Authors: | PAN Wei LIU Huan LI Guangjun |
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| Affiliation: | School of Communication and Information Engineering;Univ.of Electronic Science and Technology of China;Chengdu 610054;P.R.China |
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| Abstract: | A novel reconfigurable FFT architecture based on dynamic partial reconfiguration(DPR) was proposed.Compared with conventional FFT,the design is greatly improved in reconfigurable time.Meanwhile,reconfigurable units can be dynamically added to or removed from the processor.The reconfigurable parts features small size due to the use of the novel FFT control arithmetic.Simulation on Xilinx Virtex2p FPGA showed that the architecture has higher computing efficiency than Xilinx IPcore and exclusive characteristic... |
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| Keywords: | FPGA |
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