An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data is also presented which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.     

Split inherent-capacitive load model for CMOS buffer design

CMOS buffers are made up of a series of tapered inverters with each inverter driving a larger inverter. A split inherent-capacitance load model has been used in the design of tapered buffers, giving an improved value for the optimum taper factor between inverter stages. The overall buffer propagation delay and output transition time so obtained are smaller than those obtained using the split-capacitive load buffer model, but there is a small increase in area and power dissipation.     

Design of CMOS tapered buffer for minimum power-delay product

The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5~2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3~5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE     

Effects of simultaneous switching noise on the tapered bufferdesign

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay     

Design of tapered buffers with local interconnect capacitance

This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C³RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore, the propagation delay of each buffer stage also remains constant. Reductions in power dissipation of up to 22% and reductions in active area of up to 46%, coupled with reductions in propagation delay of up to 2%, as compared with tapered buffers which neglect local interconnect capacitance, are exhibited for an example buffer system     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的.     

Delay analysis of buffer inserted sub-threshold interconnects

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.     

使用变比例到定比例的方法优化CMOS串联缓冲器链的设计

本文提出了一种新的变比例到定比例(variable to fixed,VF)的CMOS串联缓冲器链的设计方法.这种VF的设计方法考虑了一个由倒相器组成的缓冲器链的初始输入波形斜率对其每一级时延的影响.同时,计算了倒相器的前馈电容对时延的影响.并着重研究了以上因素所导致的缓冲器链前几级的特殊性质,并据此提出了一个考虑初始波形的全局的倒相器链的优化方法.对每个倒相器的输出响应,我们提出了一组解析表达式.理论推导和SPICE的模拟证明,我们的VF设计方法是一个针对时延的最优解,面积相应较小.实验数据显示:与传统的常比例方法相比,可以节省6~10%的时延和30~70%的面积.     

基于最小延迟限度的VLSI缓冲器功耗优化设计

本文在研究ＶＬＳＩ缓冲器优化设计中关于延迟和功耗的基础理论基础上,基于高性能ＶＬＳＩ系统的非线性特性,给出了关于优化缓冲器延迟,尺寸和功耗设计以及驱动负载之间的关系,给出了基于最小延迟限度,获取缓冲器最优功耗的设计方法,可使缓冲器性能明显提高。经ＳＰＩＣＥ模拟,说明设计模型和优化设计结果是可行和较理想的。     

优化VLSI缓冲器功耗的设计模型研究

对优化超大规模集成（ＶＬＳＩ）缓立足点顺的功耗进行了研究,夺于驱动较大负载,在满足缓冲器延迟限度范围内实现系统功耗的最小化,是提高ＶＬＳＩ缓立足点顺性能的关键问题之一,文章发展了关于缓冲器信号延迟、功耗功间的关系,并给出了基于最小延 基础上缓立足点顺功耗的优化设计模型和方法。经ＳＰＩＣＥ模拟验证,该模型苛有效地降低系统功耗和提高系统工作性能,文章贪赃划合理和可行的。     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。     

混合缓存型异步光分组交换的一种改进FF-VF算法

光纤延迟线（FDL）是异步光分组交换（OPS）采用的时域冲突解决方案,通过计算其分组丢失率（PLR）发现,在业务负载高,特别是业务负载大于0．7时,PLR性能较差。研究以FDL作为主要的常规缓存、以电存储器作为辅助缓存的光电混合缓存结构,并用改进的首选即中的填空（IFF-VF）算法调度冲突的分组,达到改善可变长OPS的PLR目的。分析和仿真结果表明,光电混合缓存和IFF-VF算法能改善可变长OPS在负载较高时的PLR性能,并减少FDL的数目。     

Compact and Harmonic Suppression Wilkinson Power Divider With Short Circuit Anti-Coupled Line

A compact Wilkinson power divider using a short circuit anti-coupled line for harmonic suppression is presented in this letter. The structure consists of a pair of anti-coupled line short circuited by a capacitive load realized by a low impedance line. It can offer three finite attenuation poles in the stopband, while arbitrary phase shift can be obtained in the passband. Design procedures have been clearly presented. A 1.8-GHz power divider is designed, fabricated and measured for demonstration. It agreed well with the simulated results. The circuit area of the proposed divider is only 40% of that of the conventional one. Furthermore, the proposed divider has spurious pass-band suppression as high as 20dB.     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

一种用于LCD驱动的低功耗输出缓冲放大器

在AB类输出级的基础上,结合正反馈辅助的B类输出级,提出了一种用于LCD驱动电路的大输出摆率、低功耗的输出缓冲放大器。在0.15μm高压CMOS工艺模型下,该放大器能够驱动0～20nF范围的容性负载,静态电流为7μA,1%精度建立时间小于6μs,满足了LCD驱动电路行建立时间的要求;通过采用共源共栅频率补偿结合输出零点补偿技术,较好地满足了大动态范围容性负载的要求。     

A Drop and Throttle Flow Control Policy for Computer Networks

Store-and-forward packet switched networks are subject to congestion under heavy load conditions. In this paper a distributed drop and throttle flow control (DTFC) policy based on a nodal buffer management scheme is proposed. Two classes of traffic are identified: "new" and "transit" traffic. Packets that traveled over one or more hops are considered as transit packets. Packets that are candidates to enter the communication network are considered as new packets. At a given node if the number of allocated buffers is greater than a limit value, then new traffic is rejected, whereas transit traffic is accepted. Indeed, if the total buffer area is occupied, transit traffic is also rejected and, furthermore, it is dropped from the network. This policy is analyzed in the context of symmetrical networks. A queueing network model is developed whereby network throughput is expressed in terms of the traffic load, the number of buffers in a node and the DTFC limit value. Optimal policies where the limit value is a function of the traffic load are found to prevent network congestion. Furthermore, they achieve a very good network throughput even for loads fifty times beyond the normal operating region. Moreover, suboptimal, easy to implement fixed limit policies offer satisfactory results.     

Blocking and Delay Analysis of Single Wavelength Optical Buffer With General Packet Size Distribution

Buffers are essential components of any packet switch for resolving contentions among arriving packets. Currently, optical buffers are composed of fiber delay lines (FDL), whose blocking and delay behavior differ drastically from that of conventional RAM at least two-fold: 1) only multiples of discrete time delays can be offered to arriving packets; 2) a packet must be dropped if the maximum delay provided by optical buffer is not sufficient to avoid contention, this property is called balking. As a result, optical buffers only have finite time resolution, which may lead to excess load and prolong the packet delay. In this paper, a novel queueing model of optical buffer is proposed, and the closed-form expressions of blocking probability and mean delay are derived to explore the tradeoff between buffer performance and system parameters, such as the length of the optical buffer, the time granularity of FDLs, and to evaluate the overall impact of packet length distribution on the buffer performance.     

Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations