DC/DC辐照损伤与VDMOS器件1/f噪声相关性研究

通过对DC/DC转换器低频噪声测试技术以及在γ辐照前后电性能与1/f噪声特性变化的对比分析,发现使用低频噪声表征DC/DC转换器的可靠性是对传统电参数表征方法的一种有效补充.对DC/DC转换器辐照损伤与其内部VDMOS器件1/f噪声相关性进行了研究,讨论了引起DC/DC转换器辐照失效的原因.     

光电耦合器件低频噪声特性与可靠性老化研究

在宽的输入偏置电流范围条件下,开展了光电耦合器件低频噪声特性测试与功率老化和高温老化的可靠性试验研究。结果表明,光电耦合器件的低频噪声主要是内部光敏晶体管1/f噪声,并随输入偏置电流的增大呈现先增大后减小的规律,这与器件的工作状态密切相关。功率老化试验后,高输入偏置电流条件下的低频噪声有所增大,这归因于电应力诱发的有源区缺陷。高温老化试验后,整个器件线性工作区条件下的低频噪声都明显增大,说明温度应力能够更多地激发器件内部的缺陷。相对于1/f噪声幅度参量,低频噪声宽带噪声电压参量可以更灵敏准确地进行器件可靠性表征。     

CMOS反相器低频噪声模型及可靠性表征研究

为了表征CMOS反相器的可靠性,从其负载电流和输出电压的特性入手,详细推导了一种基于载流子波动理论的低频噪声模型,并由实验数据验证了模型的准确性.由实验结果可知,负载电流功率谱密度随频率的增加而减小,遵循1/f噪声的变化规律;得到了负载电流归一化噪声功率谱密度与器件尺寸的关系.通过深入研究1/f 噪声与界面态陷阱密度的关系,验证了1/f噪声可用于表征CMOS反相器的可靠性,证明了噪声幅值越大,器件可靠性越差,失效率显著增大,为评价CMOS反相器的靠性提供了一种可行及有效的方法.     

MOSFET1/f噪声相似性的子波鉴别方法

基于傅里叶分析的功率谱密度只能反映1/f噪声的整体频率特性,子波变换模极大值能够反映1/f噪声的奇异性和非规整性,而后者才是1/f噪声最本质的特征所在.本文将这一特性用于MOSFET 1/f噪声的相似性分析.从子波变换模极大值匹配原理出发,定义了一个1/f噪声的相似系数,利用它对不同形成机制、不同微观缺陷状态、不同偏置应力作用下的MOSFET 1/f噪声进行了相似性分析,发现它可作为鉴别1/f噪声的物理起源,分析1/f噪声的微观动力学机制,筛选有潜在缺陷或损伤的MOS器件的有效手段.     

用于DC／DC转换器的肖特基二极管^60Co γ辐照实验研究

对DC／DC电源模块中的肖特基二极管进行了^60Co γ辐照实验，详细研究其正反向特性和1/f噪声的总剂量效应。实验发现，辐照没有明显引起正向特性变化，但使得反向击穿电压减小，漏电流变大，1／f噪声剧烈增加。基于隧穿效应的分析表明，发现辐照诱生新的界面态及界面态密度分布的变化调制了肖特基势垒高度，是引起器件性能退化主要原因。     

光电耦合器电流传输比的噪声表征

光电耦合器中可俘获载流子的陷阱密度是影响其电流传输比(CTR)的重要因素,并与器件可靠性有密切关系.在器件内部的多种噪声中,1/f噪声可有效地表征器件陷阱密度.本文在研究光电耦合器工作原理以及1/f噪声理论的基础上,建立了光电耦合器的CTR表征模型和1/f噪声模型.在输入电流宽范围变化的条件下,测量了器件的电学噪声和CTR变化,实验结果验证了以上模型的正确性.将CTR模型与噪声模型相结合,得到了CTR与1/f噪声之间的关系.此关系应用于对光电耦合器辐照实验结果的分析,实验结果与理论得到的结论一致.理论与实验结果表明,噪声幅值越大,电流指数越接近于2,则器件的可靠性越差,相同工作条件下CTR的老化衰减量越大,其失效率显著增大.从而证明噪声可表征光电耦合器的CTR并能准确地反映器件的可靠性.     

光电耦合器电流传输比的噪声表征

光电耦合器中可俘获载流子的陷阱密度是影响其电流传输比(CTR)的重要因素,并与器件可靠性有密切关系.在器件内部的多种噪声中,1/f噪声可有效地表征器件陷阱密度.本文在研究光电耦合器工作原理以及1/f噪声理论的基础上,建立了光电耦合器的CTR表征模型和1/f噪声模型.在输入电流宽范围变化的条件下,测量了器件的电学噪声和CTR变化,实验结果验证了以上模型的正确性.将CTR模型与噪声模型相结合,得到了CTR与1/f噪声之间的关系.此关系应用于对光电耦合器辐照实验结果的分析,实验结果与理论得到的结论一致.理论与实验结果表明,噪声幅值越大,电流指数越接近于2,则器件的可靠性越差,相同工作条件下CTR的老化衰减量越大,其失效率显著增大.从而证明噪声可表征光电耦合器的CTR并能准确地反映器件的可靠性.     

用1/f噪声表征VDMOS器件的抗辐照性能

介绍了用于航空航天DC/DC转换器中的VDMOS器件和电离辐照前后低频1/f噪声的变化.研究了电离辐照情况下VDMOS器件的阈值电压漂移、跨导的退化对1/f噪声幅值、γ值的影响.结合实验,比较器件1/f噪声幅值和γ值在辐照前后的变化,对其抗辐照性能做表征研究.对VDMOS器件在辐照前后的变化做了分析,从γ值分形的角度简要说明辐照对器件产生的影响.     

混合模式电应力损伤对SiGe HBT器件1/f噪声特性的影响研究

研究了混合模式应力损伤对SiGe HBT器件直流电性能的影响,对比了混合模式损伤前后器件1/f噪声特性的变化。结果表明,在SiGe HBT器件中,混合模式损伤在Si/SiO₂界面产生界面态缺陷P_b,导致小注入下基极电流增加;H原子对多晶硅晶界悬挂键的钝化作用引起中等注入区基极电流减小,导致电流增益增强。混合模式损伤缺陷位于硅禁带宽度内本征费米能级附近,虽然使基区SRH复合电流增加,却不会改变器件的低频噪声特性。     

先进MOSFET中1/f噪声研究进展

全面综述了先进金属氧化物半导体场效应晶体管(MOSFET)的1/f噪声研究进展。界面态、器件结构、材料缺陷、量子效应等诸多因素均会影响1/f噪声。随着工艺尺寸的持续缩小和高k介质材料的应用,以及热载流子效应、辐照损伤等因素的影响,MOSFET的1/f噪声起源问题一直是学术界具有较大分歧和争议的课题。只有澄清了1/f噪声的真正物理起源,才能有效通过工艺加以改善,支撑设计应用。     

SONOS结构EEPROM单元辐射效应分析

随着EEPROM存储器件在太空和军事领域的广泛应用,对EEPROM抗辐射性能的研究越来越多。为了满足应用的需要,文章比较了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,分析了FLOTOX和SONOS单元抗辐射性能的优劣,得出:SONOS结构的EEPROM单元,其抗辐射性能优于FLOTOX结构。并分析了在辐射条件下,SONOS结构受辐射影响的数学模型。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM研究提供了理论基础。     

Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture

In this letter, we present SONOS nonvolatile memory device with gate-all-around polycrystalline silicon (poly-Si) nanowire channel. The SONOS memory cell with 23-nm nanowire width, fabricated using top-down CMOS process, exhibits fast programming and erasing speed as well as improved subthreshold behavior of the transistor. Both the memory and transistor characteristics are dependent on the nanowire width—smaller the width, better the performance. The good device characteristics along with simple fabrication method make the poly-Si nanowire SONOS memory a promising candidate for future system-on-panel and system-on-chip applications.      

EEPROM单元辐射机理研究

随着EEPROM存储器件在太空和军事领域的广泛应用,国际上对EEPROM抗辐射性能的研究越来越多。为了满足太空及军事领域的需要,文章分别研究了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,比较了FLOTOX和SONOS单元抗辐射性能的优劣,得出由于FLOTOX单元受工艺和结构的限制,抗辐射性能不如SONOS单元。同时在做抗辐射加固设计时,FLOTOX单元还需要考虑到电压耦合比的问题,且不利于等比例缩小。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM制作提供了理论基础。     

On the go with SONOS

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for nor-type Flash Memory

A dopant-segregated Schottky barrier (DSSB) FinFET silicon–oxide–nitride–oxide–silicon (SONOS) for nor-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant-segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for nor-type Flash memory with high-speed and low-power programming.      

SONOS非挥发性存储器件的研究进展

随着非挥发性存储器件的尺寸持续缩小,SONOS结构存储器件又重新被重视.简单介绍超短栅长SONOS器件和2 bit SONOS器件,重点介绍改进氮化硅层和应用high-K材料,来改善SONOS器件性能的研究.认为只要解决high-K材料在非挥发性存储器件中的应用,具有好的发展前景.     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

A novel omega-shaped-gated (Ω-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Ω-Gate structure inherently covered two sharp corners manufactured simply via a sidewall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Ω-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Ω-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Ω-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications.     

Effects of two-step high temperature deuterium anneals on SONOSnonvolatile memory devices

The deterioration of the Si-SiO₂ interface is associated with the degradation of long-term retention in polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) devices. Two-step high temperature deuterium anneals, applied in SONGS device fabrication for the first time, improves the endurance characteristics and retention reliability over traditional hydrogen anneals. Electrical characterization shows deuterium-annealed SONOS devices have nearly one order of magnitude longer retention time than hydrogen-annealed devices after 10⁷ erase/write cycles at 85°C to provide an extrapolated 0.5 V detection window at ten years