双外延基区BJT基区渡越时间的模型研究

The doping profile function of a double base epilayer is constructed according to drift-diffusion theory. Then an analytical model for the base transit time τb is developed assuming a small-level injection based on the characteristics of the 4H-SiC material and the principle of the 4H-SiC BJTs. The device is numerically simulated and validated based on two-dimensional simulation models. The results show that the built-in electric field generated by the double base epilayer configuration can accelerate the carriers when transiting the base region and reduce the base transit time. From the simulation results, the base transit time reaches a minimal value when the ratio of L2/L1 is about 2.     

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_t2 of the HBT trigger SCR is 80% more than that of the MLSCR.     

垂直隧穿场效应晶体管的亚阈值特性分析

Subthreshold characteristics of vertical tunneling field effect transistors(VTFETs) with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.     

增加衬底电阻提高高压多指GG-nLDMOS器件的均匀导通性

With the impact of the non-uniform turn-on phenomenon,the ESD robustness of high-voltage multifinger devices is limited.This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GGnLDMOS device.By means of increasing substrate resistance,an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS.This approach has been successfully verified in a 0.35 m 40 V BCD process.The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness.     

A novel approach for justification of box-triangular germanium profile in SiGe HBTs

This work presents a unique and robust approach for validation of using the box-triangular germanium profile in the base of SiGe heterojunction bipolar transistors, where the methodology considers the simultaneous optimization of the p-type base doping profile in conjunction with the germanium profile in the base. The study analyses the electron motion across the SiGe base in SiGe HBTs, owing to different accelerating electric fields. The analysis first presents a figure of merit, to achieve the minimum electron transit time across the base in conjunction with the increased current gain in n–p–n-SiGe HBTs, which shows a general trend vis-à-vis the advantage of a trapezoid germanium profile, but with additional accuracy as we considered simultaneously optimized p-type base doping. The effect of minority carrier velocity saturation is then included to make the study more detailed. The analysis then investigates the shifted germanium profile in the base to further minimize the base transit time. Finally,it is shown that a shifted germanium profile eventually evolves into a box-triangular Ge-profile in the SiGe base,which could simultaneously minimize the base transit time and reduce emitter delay by virtue of the high current gain. The analysis verifies that for an average Ge-dose of 7.5% Ge across the base, a box-triangular germanium profile in conjunction with an optimum base doping profile has an approximately identical base transit time and a 30% higher current gain, in comparison with an optimum base doping and triangular Ge-profile across the whole base.     

一种高速雪崩光电探测器

High-speed avalanche photodiodes are widely used in optical communication systems. Nowadays, separate absorption charge and multiplication structure is widely adopted. In this article, a structure with higher speed than separate absorption charge and multiplication structure is reported. Besides the traditional absorption layer, charge layer and multiplication layer, this structure introduces an additional charge layer and transit layer and thus can be referred to as separate absorption, charge, multiplication, charge and transit structure. The introduction of the new charge layer and transit layer brings additional freedom in device structure design. The benefit of this structure is that the carrier transit time and device capacitance can be reduced independently, thus the 3 dB bandwidth could be improved by more than 50% in contrast to the separate absorption charge and multiplication structure with the same size.     

Characterization analysis of UDSM LVTSCR under TLP stress

The characteristics of a low-voltage triggering silicon-controlled rectifier(LVTSCR) under a transmission line pulse(TLP) and the characteristics of high frequency are analyzed.The research results show that the anode series resistance has a significant effect on the key points of the snapback curve.The device characteristics can fit the requirements of a electrostatic discharge(ESD) design window by adjusting the anode series resistance. Furthermore,the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR.A steep rising edge will cause the turn-on voltage to increase.The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance,and its accuracy calculation is very important to the ESD design of high frequency circuits.Our research results provide a theoretical basis for the design of an ultra-deep sub-micron(UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.     

Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

90纳米CMOS工艺下带改进RC网络的电源轨静电泄放箝位电路

An electrostatic discharge(ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed.The leakage current is reduced to 4.6 nA at 25℃.Under the ESD event,it injects a 38.7 mA trigger current into the P-substrate to trigger SCR,and SCR can be turned on the discharge of the ESD energy.The capacitor area used is only 4.2μm~2.The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency,compared with the previous circuits.     

SOI基蓝紫光敏感光电探测器的设计与模拟

According to Lambert’s law,a novel structure of photodetectors,namely photodetectors in siliconon-insulator,is proposed.By choosing a certain thickness value for the SOI layer,the photodetector can absorb blue/violet light effectively and affect the responsivity of the long wavelength in the visible and near-infrared region,making a blue/violet filter unnecessary.The material of the SOI layer is high-resistivity floating-zone silicon which can cause the neutral N type SOI layer to become fully depleted after doping with a P type impurity.This can improve the collection efficiency of short-wavelength photogenerated carriers.The device structure was optimized through numerical simulation,and the results show that the photodiode is a kind of high performance photodetector in the blue/violet region.     

New fast turn-on speed SCR device for electrostatic discharge protection

A new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed to improve the turn-on speed for electrostatic discharge (ESD) protection. The turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR, and the VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the VSCRs with the VLBD structure is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.     

一种用于静电保护的快速开启SCR器件

提出了一种用于提高静电泄放(ESD)保护器件开启速度的SCR器件(VSCR)。VSCR采用了新型的横向基区变掺杂结构(VLBD),其开启速度主要由寄生p-n-p和n-p-n晶体管的基区渡越时间决定,使用VLBD结构能够减小寄生双极型晶体管的基区渡越时间,从而提高SCR器件的开启速度。实验结果证明,在不增加掩膜版数量和芯片面积的前提下,相比于传统均匀基区掺杂的MLSCR器件,采用VLBD结构的VSCR器件的开启速度能够提高12%。     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier (DTSCR) is widely used for electrostatic discharge (ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse (TLP) test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multiple-triggering effect.     

High speed integrated injection logic (I/SUP 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.     

一种快速开启的低触发改进型DTSCR

提出了一种快速开启的低触发改进型DTSCR(MDTSCR)。该MDTSCR是在传统DTSCR基础上加入电流增益放大模块,大幅提升了寄生双极型晶体管的电流增益,降低触发电压,提高了器件的开启速度。实验结果表明,在28 nm CMOS工艺下,与传统DTSCR相比,该MDTSCR的开启时间缩短了52%,触发电压从5.5 V下降到4.5 V。该MDTSCR通过调整二极管数目适应28 nm CMOS工艺不同的设计窗口,获得了最优的防护性能。     

New insulated-gate thyristor structure with MOSFET coupled baseregions

A new insulated-gate thyristor (IGTH) structure in which the base of n-p-n transistor is coupled to the base of p-n-p transistor through a MOSFET is described for the first time, In the new structure, called base coupled insulated gate thyristor (BC-IGTH), the parasitic lateral p-n-p carrier injection inherent in previously reported thyristor structures such as the MCT, BRT, and IGTH is absent. The absence of parasitic lateral p-n-p carrier injection results in low on state voltage drop and high controllable current capability for this structure. The turn-on process in the new structure is fundamentally different from other MOS-gated thyristor structures in that in the new structure, the higher gain n-p-n transistor is turned-on first, which then provides the base drive for the lower gain p-n-p transistor. Multicellular 800 V devices of the new thyristor structure were fabricated using a double-diffused DMOS process, and were found to give on-state drop of 1.1 V at 200 A/cm², and controllable currents in excess of 100 A/cm² were obtained by forming MOS-gate controlled emitter-to-base resistive shorts     

Lateral complementary transistor structure for the simultaneous fabrication of functional blocks

Heretofore, the schemes for fabricating a complementary transistor structure in a monolithic functional block entailed either some additional, difficult-to-control processing steps or a sacrifice in isolation of the collector regions of one type of transistor. This paper describes an isolated p-n-p transistor structure fabricated by the same technique used for the conventional all n-p-n transistor functional block without any additional processing steps. The basic p-n-p transistor has a lateral structure. During the p-type base diffusion of the n-p-n transistor, two concentric p-type regions at close distance are selectively diffused into an isolated n- type region such as that used for the collector of an n-p-n transistor. The center p-type diffused region forms the emitter and the outer ring forms the collector. The n-type spacing between these two regions serves as the base. The current gain of this transistor is not high, typically around unity. However, by amplifying the collector current of the p-n-p transistor with an n-p-n transistor, the composite transistor acts like a high gain p-n-p transistor and the composite current gain can be made comparable to that of the n-p-n transistor in the same functional block. The lateral complementary transistor has been used extensively and successfully for the fabrication of linear functional blocks such as those used in the Advanced Minuteman Program.     

The use of an interface anneal to control the base current andemitter resistance of p-n-p polysilicon emitter bipolar transistors

The effects of an interface anneal on the electrical characteristics of p-n-p polysilicon-emitter bipolar transistors are reported. For devices with a deliberately grown interfacial oxide layer, an interface anneal at 1100°C leads to a factor of 15 increase in base current, and a factor of 2.5 decrease in emitter resistance, compared with an unannealed control device. These results are compared with identical interface anneals performed on n-p-n devices, and it is shown that the increase in base current for p-n-p devices is considerably smaller than that for the n-p-n devices. This result is explained by the presence of fluorine in the p-n-p devices, which accelerates the breakup of the interfacial layer     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent