Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.     

How to improve intrinsic and extrinsic reliability of vias by process optimization

A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed.     

Stabilization of sheet resistance for metal lines by formation of etch stop layer (ESL) trench structure

Sheet resistance of metal lines is mainly affected by critical dimension (CD), etch depth, and chemical mechanical planarization amount in damascene process. Therefore, these factors must be stably controlled in order to stabilize the sheet resistance of metal lines. Especially the etch depth, which is sensitive to the pattern density and the equipment conditions bring not only the variation of sheet resistance of metal lines but also the connection problem to the under-layered contacts. The objective of this study is to reduce the variation of the sheet resistance of metal lines by stabilization of the etch depth with etch stop layer (ESL). SiN film was used as an ESL while the intermetal dielectric (IMD) films were employed by the conventional fluorine-doped silicate glass (FSG)/SiH₄ film with an increment of thickness by the employment of SiN film as an ESL. The selectivity of oxide-to-nitride was about 6.4:1 for etch stop step. While the stop layers were removed after the etch stop step, the pre-metal dielectric was also etched at the same time for the stable connection to the under-layered contacts. Comparing the ESL method to the conventional method, more stable metal lines were formed with the in-line CD measurement, thickness measurement, cross-sectional scanning electron microscopy analysis, and sheet resistance measurement from the view point of the connection to the under-layered contacts. The stable sheet resistance of metal lines was also obtained with the changes in etch time or thickness.     

A direct measurement of electromigration induced drift velocity in Cu dual damascene interconnects

A dual damascene structure with an additional 25 nm Ta diffusion barrier embedded into the upper Cu layer was fabricated to measure the drift velocity of electromigration. The embedded diffusion barrier layer successfully confined void growth into a long and regular shape between the SiN layer and embedded Ta layer. Edge depletion was observed to initiate from the cathode end and elongate into a long and regular shape due to the confinement of the intermediate Ta diffusion barrier layer. With this test structure, electromigration induced drift displacement can be accurately measured with a linear dependence on time. Measurement was conducted at a series of temperatures to obtain the Cu/capping interface diffusion controlled activation energy.     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

Reduced Cu interface diffusion by CoWP surface coating

Electromigration in Cu interconnections with a 10-nm thick selective electroless CoWP coating on the top surface of Cu dual damascene lines has been investigated. The grain structures of the lines embedded in SiLK semiconductor dielectric ranged from bamboo-like to polycrystalline. CoWP coated structures exhibited a greatly improved Cu electromigration lifetime which was attributed to a reduction in Cu interface diffusion.     

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.     

Analysis of Cu/Low-k structure under back end of line process

As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global-local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global-local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.     

AlN/GaN Insulated-Gate HFETs Using Cat-CVD SiN

The authors fabricated SiN/AlN/GaN metal–insulator–semiconductor heterostructure field-effect transistors (MIS-HFETs) using SiN passivation by catalytic chemical vapor deposition (Cat-CVD). Cat-CVD SiN increased the electron density of AlN/GaN HFETs by compensating the surface depletion of the two-dimensional electron gas. The MIS-HFETs had a maximum drain current density of 0.95 A/mm and a peak extrinsic transconductance of 211 mS/mm. A current-gain cutoff frequency of 107 GHz and maximum oscillation frequency of 171 GHz were obtained for the 60- and 70-nm-gate devices, respectively.     

Diffusion barrier integrity and electrical performance of Cu/porous dielectric damascene lines

One issue accompanying the introduction of porous dielectrics in Cu damascene interconnects is the integrity of diffusion barriers. For the first time a direct correlation is shown between the physical integrity of the barrier layer and the electrical performance of damascene lines embedded in a dielectric with a k value of 2.0. The breakdown field at 100/spl deg/C for lines with a porous barrier layer is considerably lower than that for lines with an efficient sealing barrier. Irreversible degradation is also observed in the leakage current of structures with a porous barrier after thermal and electrical stress. Contamination of the porous dielectric can take place already during damascene processing, so the use of a barrier layer that can efficiently seal the pores after dielectric patterning is essential for a proper functioning of future interconnects.     

铜互连线内电流拥挤效应的影响

提出了一种新的测试结构(S结构),通过实验、理论推导和有限元分析,研究了铜与TaN扩散阻挡层界面的电流拥挤效应对电迁移致质量输运特性的影响.实验和有限元分析表明,铜互连线内由于电流拥挤效应的存在,在用户温度下沿特定通道输运的局部原子通量显著增大,而焦耳热所产生的温度梯度对原子通量和通量散度增大的影响则相对有限.     

Experimental results on the integration of copper and CVD ultra low k material

The integration of ultra low k materials in copper damascene architecture is one of the main issues in finding microelectronic-process-compatible dielectric materials. The aim of this paper is to show the integration conformity with common equipment and process steps using a PECVD (plasma enhanced chemical vapor deposition) CF polymer ultra low k material in a Cu single damascene architecture (Proceedings of the Advanced Metallization Conference, 2002). The intermetal dielectric low k material used in the described structures has 2.1≤k≤2.3 (k depends on deposition process parameters [Microelectron. Eng. 50 (2000) 7–14]) and the copper was deposited by a metal organic chemical vapor deposition process. After chemical mechanical polishing the structures were characterized by scanning electron microscopy and electrical measurements.     

Electromigration lifetimes and void growth at low cumulative failure probability

We have investigated electromigration (EM) lifetimes and void formation at cumulative failure probability of around 50 ppm. We carried out EM test in damascene Cu lines using sudden-death test structures. Cumulative failure probability of the test ranges from 50 ppm to 90%. To investigate the void nucleation and growth behaviour, Cu microstructures were investigated by using scanning transmission electron microscopy (S-TEM) and electron backscatter diffraction (EBSD) technique. EM lifetime shows strong correlation with the void nucleation site and the void volume. In addition, the worst case for EM lifetime is that wide angle grain boundary exists just under the via as a void nucleation site.     

Process improvement of 0.13 μm Cu/Low K (Black Diamond) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

SILK compatibility with the IMD process using copper metallization

This work presents the results of SILK compatibility with the materials used in the damascene structure with copper metallization. Firstly, the thermal stability of the material was carefully evaluated; excellent stability at 450°C was confirmed. Moreover, 450°C is a good curing temperature for obtaining a low dielectric constant (2.7). The conventional PECVD hard masks, SiO₂ (from SiH₄ or TEOS precursors) and Si_xN_y do not affect the SILK properties. Finally, it was verified that an OMCVD TiN barrier is efficient in preventing copper diffusion. It was demonstrated that SILK should reach the performance requested for IMD materials in the damascene structure with Cu metallization.     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.