电流拥挤效应对GaN基发光二极管可靠性的影响

文中报道了绝缘蓝宝石衬底上的GaN基发光二极管（LEDs）中，由于横向电阻的存在造成了靠近n型电极台面边缘局部区域电流拥挤，为此从焦耳热和金属电迁移两方面研究了电流拥挤效应对器件可靠性的影响，加速寿命实验结果表明：电流均匀扩展可以使可靠性得到有效改善。     

Sn-Ag-Cu无铅钎料互连焊点的电迁移研究进展

电迁移问题作为影响焊点可靠性的关键问题之一,容易导致焊点出现裂纹、丘凸和空洞等焊接缺陷.其失效机制有电流拥挤效应、焦耳热效应、极化效应和金属间化合物失效等.聚焦Sn-Ag-Cu系无铅钎料焊点的电迁移问题,介绍了这一领域电迁移的失效机制、影响因素和防止措施的研究现状,并展望了今后的研究发展趋势.     

InGaN/GaN多量子阱LED的电特性研究

针对InGaN/GaN多量子阱LED,分析了占据能态高于势垒的载流子和低于势垒的载流子参与的电流输运机制,从而推导出对应能态电流输运机制下的电流-电压关系,以及理想因子与温度的变化规律.实验结果证实,在低注入强度下,由材料缺陷引入的深能级辅助隧穿输运机制占主导,电流电压特性符合相应的推导结果,随着注入强度的增大,参与扩散-复合输运机制的载流子逐渐增加,温度对输运机制的影响逐渐增大.     

GaN基HEMT器件的表面陷阱电荷输运过程实验研究

基于特制的无台面AlGaN/GaN HEMT,设计了一种实验方法,用以研究AlGaN/GaN外延表面陷阱态间的电荷输运过程。经实验证实,在器件电流崩塌效应中,存在表面陷阱电荷输运,并确定了相关时间常数。针对应力后电流崩塌驰豫过程,实验监测到小于0.1 s和大于10 s两类时间常数,其中较大的常数对应于表面陷阱电荷的输运过程。此结论可望用于对AlGaN/GaNHEMT电流崩塌效应进一步的理论探索和相关的器件研究。     

有机电致发光薄膜的电流输运机理的分析

用TPD作空穴传输层、8－羟基喹啉锌作发光层,制备了有机薄膜器件,测量了其电致发光特性。分析了该器件的电流输运机理,认为该有机薄膜器件在电致发光时流过器件的电流受热电子注入效应、空间电荷限制效应、隧穿效及器件电阻效应的影响。     

基于自动建模方法的互连可靠性分析

金属互连线中的电迁移现象是导致互连线失效的主要原因,影响电迁移(EM)的因素有温度、电流、材料特性和互连线的几何尺寸等。采用有限元分析方法,探究导致电迁移的这些因素的工作机制,以及这些机制之间的相互影响,并且采用原子通量散度(AFD)来衡量电迁移的大小。使用先进的自动建模并仿真的方法,得到互连线的材料属性、几何尺寸、电流密度,以及外界环境温度与AFD的关系,通过AFD的变化规律分析互连线的可靠性。结果表明,温度升高、电流增大、尺寸减小,都会降低互连线的可靠性。     

无铅焊料的电迁移效应

电迁移是金属原子沿着电流方向的移动。本文阐述了无铅焊料中电迁移的物理特性,由于焊点的特殊几何形状,电流拥挤效应将发生在焊点与导线的接点处;电迁移效应导致无铅焊料中金属间化合物（IMC）的生成与溶解,以及焊点下的金属化层（UBM）的溶解和消耗,使原子发生迁移并会产生孔洞,造成焊点破坏,缩短了焊点平均失效时间（MTTF）,从而带来可靠性问题。     

无铅焊料的研究（4）——电迁移效应

电迁移是金属原子沿着电流方向的移动。阐述了无铅焊料中电迁移的物理特性,由于焊点的特殊几何形状,电流拥挤效应将发生在焊点与导线的接点处;电迁移效应导致无铅焊料中金属间化合物(IMC)的生成与溶解,以及焊点下的金属化层(UBM)的溶解和消耗,使原子发生迁移并会产生孔洞,造成焊点破坏,缩短了焊点平均失效时间(MTTF),从而带来可靠性问题。     

氮掺杂对单壁碳纳米管的非平衡电子输运特性的影响

利用结合了非平衡格林函数的第一性原理的局域密度泛函理论,研究了氮原子取代掺杂单壁碳纳米管的输运特性.计算结果表明,不同构形和不同数目的氮原子掺杂对(8,0)单壁碳管的输运性能有复杂的影响.研究发现,氮原子的掺杂提高了半导体型碳管的输运性能,电流-电压曲线呈非线性变化.对于浓度相同的氮掺杂,原胞内最近邻氮原子间距极大地影响了碳管的输运性能.因此,基于掺杂管的分子器件的设计中很有必要考虑这些因素.     

氮掺杂对单壁碳纳米管的非平衡电子输运特性的影响

利用结合了非平衡格林函数的第一性原理的局域密度泛函理论,研究了氮原子取代掺杂单壁碳纳米管的输运特性.计算结果表明,不同构形和不同数目的氮原子掺杂对(8,0)单壁碳管的输运性能有复杂的影响.研究发现,氮原子的掺杂提高了半导体型碳管的输运性能,电流-电压曲线呈非线性变化.对于浓度相同的氮掺杂,原胞内最近邻氮原子间距极大地影响了碳管的输运性能.因此,基于掺杂管的分子器件的设计中很有必要考虑这些因素.     

Enhanced finite element modelling of Cu electromigration using ANSYS and matlab

An enhanced finite element modeling methodology based on commercial software ANSYS Multi-physics and Matlab is developed for the study of electromigration. Various driving forces, namely electron wind force migration (EWM), thermomechanical stress gradient induced migration (SM) and temperature gradient induced migration (TM) are simulated and the resulting atomic flux of metal atoms is calculated based on a non-standard use of ANSYS static thermal analysis routine. An automatic link between ANSYS and Matlab is developed to enhance the capability of ANSYS data postprocessing module in the calculation of atomic flux divergence (AFD). The simulation of a polycrystalline Cu thin film identifies a new potential EM reliability hazard in Cu interconnects which agrees well with experimental observations.     

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.     

Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures

Atomic flux divergence (AFD) based finite element analyses have been performed to show the difference in the electromigration (EM) failure mechanisms at different test conditions for Cu dual damascene line-via test structures. A combined driving force approach adapted in the model consists of driving forces from electron-wind, stress-migration and thermo-migration. It is shown that the failure mechanisms depend on the test condition and the stress free temperature of the structure. As the failure time depends on the failure mechanisms, the life-time prediction from accelerated test would be inaccurate if the invariability of failure mechanisms is assumed. It is also found that the interconnect life-time can be improved by lowering the final annealing temperature of the structure.     

Finite element modeling on electromigration of solder joints in wafer level packages

This work studies the electromigration of solder joints in an encapsulated copper post wafer level package (WLP) by finite element modeling. Experimental data showed that the electromigration failure occurs in solder joints on the printed circuit board (PCB) side due to the current crowding. In order to improve the electromigration performance on the PCB side with a copper post WLP, two new line-to-bump geometry designs are proposed. Coupled electro-thermal finite element modeling is performed to obtain the electrical and thermal fields simultaneously. The ionic flux from electron wind and thermal response is calculated based on finite element solutions. The divergence of the total flux, which is the sum of the divergence of electromigration and thermomigration, is extracted at the critical locations in solder joints. Results show that the new proposed design structures can reduce the maximum current density by 19%, and the divergence of the total ionic flux by 42%. Thermal gradient is very small in solder joints, therefore, the main driving force for electromigration failures comes from the electron wind. The finite element results on mesh dependency are discussed in this paper.     

Characteristics of current crowding in flip-chip solder bumps

For a flip-chip package assembly, current crowding occurs in the vicinity of the locations where traces connect the solder bumps. This feature contributes significantly to the electromigration failure of the solder bumps. In this study the finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current. It is found that under such a condition, current crowding is induced solely by the structural geometry of the system. It is independent of the magnitude of the applied current. A volumetric averaging technique is also applied to cope with the current crowding singularity.     

Replacement metal-gate NMOSFETs with ALD TaN/EP-Cu, PVD Ta, and PVD TaN electrode

This work reports the first replacement (damascene) metal gate NMOSFETs with atomic layer deposition (ALD) TaN/PVD and electroplated Cu as the stacked gate electrode. Transistors with PVD TaN and PVD Ta electrode are also fabricated. Our data show that ALD TaN has the right work function for the N-MOSFETs. The Cu damascene process can reduce the gate resistivity. The ALD process has the advantage of reducing the stress and radiation damage to the gate oxide. The damascene process flow bypasses high temperature steps (>600/spl deg/C)-critical for metal gate and high-k materials.     

Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages

Solder bumps serve as electrical paths as well as structural support in a flip-chip package assembly. Owing to the differences of feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase in a significant amount. This current crowding effect along with the induced Joule heating would accelerate fatigue failure due to electromigration. In this paper we apply the three-dimensional electrothermal coupling analysis to investigate current crowding and Joule heating in a flip-chip package assembly carrying different constant electric currents under different ambient temperatures. Experiments are conducted to calibrate temperature-dependent electric resistivities of solder alloy, Al trace, and Cu trace, and to verify the numerical model by comparing calculated and measured maximum temperatures on the die surface. Through the electrothermal coupling analysis, effects of current crowding and Joule heating induced by different solder bump structures are examined and compared.     

Recent advances on kinetic analysis of electromigration enhanced intermetallic growth and damage formation in Pb-free solder joints

A comprehensive kinetic analysis was established to investigate the electromigration (EM) enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints with Cu under bump metallization (UBM). The kinetic model takes into account Cu-Sn interdiffusion and current stressing. Derivation of the diffusion coefficients and the effective charge numbers for the intermetallic compounds is an essential but challenging task for the study of this multi-phase multi-component intermetallic system. A new approach was developed to simultaneously derive atomic diffusivities and effective charge numbers based on simulated annealing (SA) in conjunction with the kinetic model. A consistent set of parameters were obtained, which provided important insight into the diffusion behaviors driving the IMC growth. The parameters were used in a finite difference model to numerically solve the IMC growth problem and the result accurately correlated with the experiment. EM reliability test revealed that the ultimate failure of the solder joints was caused by extensive void formation and subsequent crack propagation at the intermetallic interface. This damage formation mechanism was analyzed by first considering vacancy transport under current stressing. This was followed by a finite element analysis on the crack driving force induced by void formation. This paper is concluded with a future perspective on applying the kinetic analysis and damage mechanism developed to investigate the structural reliability of the through-Si-via in 3D interconnects.     

Cu互连线显微结构和应力的AFM及SNAM分析

在ULSI中采用Cu互连线代替Al以增加电子器件的传输速度和提高器件的可靠性，Cu的激活能约为1．2eV，而Al的激活能约为0．7eV,Cu互连线寿命约为Al的3－5倍。Cu大马士革互连线的制备工艺为：在硅衬底上热氧化生成的SiO2上开出凹槽，在凹槽中先后沉积阻挡层Ta和晶种层Cu，然后由电镀的Cu层将凹槽填满，最后采用化学机械抛光将凹槽外多余的Cu研磨掉，Cu互连线的尺寸为：200um长，0．5μm厚，宽度分别为0．35，0．5，1至3μm不等，部分样品分别在200℃，300℃和450℃下经过30min退火。利用原子力显微镜（AFM）和扫描近场声学显微镜（SNAM），同时获得形貌像和声像，分别了Cu大马士革凹槽构造引起的机械应力和沉积引起的热应力对Cu互连线显微结构及可靠性的影响，SNAM是在Topometrix公司AFM基础上建造的实验装置，实验采用的机械振动频率在600Hz-100kHz之间。分析测试结果如下：1．AFM和SNAM可以实现对微米和亚微米特征尺寸的Cu互连线的局域应力分布和显微结构的原位分析。2．采用AFM，TEM、XRD观察和测试了Cu互连线的晶体结构，分析了大马士革凹槽工艺 对Cu晶粒尺寸及取向的影响。平坦的沉积态Cu膜的晶粒尺寸约为100nm；而由大马士革工艺制备的凹槽中的Cu互连线的晶粒尺寸约为70－80nm，凹槽结构抑制了晶粒生长，平坦的沉积态Cu膜有较强的（111）织构；而凹槽中的Cu互连线的（111）织构减弱，（200）和其它的晶体取向分量增强。3．SNAM声阻尼信号对材料局域应力的变化敏感，SNAM声图衬底可显示出局域应力的分布，在沉积态的Cu互连线声图中，金属和SiO2介电层的界面处像衬度强，表明该处为应力较高的区域，而在退火后的Cu互连线的声图中，金属和SiO2介电层的界面处像衬度弱，表明退火后该处应力减小，我们对Cu膜进行了宏观应力的测试，退火后应力值从沉积态的661MPa减少至359Mpa，这与SNAM声成像的结果相符合。     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.