集成电路片内铜互连技术的发展

论述了铜互连取代铝互连的主要考虑,介绍了铜及其合金的淀积、铜图形化方法、以及铜与低介电常数材料的集成等。综述了ULSI片内铜互连技术的发展现状。     

低k氟化非晶碳层间介质对芯片性能的影响

讨论了通过合理设计的工艺流程将低k氟化非晶碳材料应用到制造工艺中作为互连介质对集成电路性能的影响。基于一个互连结构简化模型计算出采用低k氟化非晶碳材料作为互连介质后RC延迟、功率耗散和线间串扰的变化情况。采用低k氟化非晶碳介质后,RC延迟和功率耗散随着互连长度的增大而减小,线间串扰也得到显著抑制。     

光学互连与光电子多芯片组件

高性能的电子系统中，其内部互连网络所产生的影响对系统性能的作用表现得尤为明显。随着系统集成朝着更大规模的方向发展，电子系统内部电路的互连延迟已经成为限制其发展的主要障碍之一。光互连技术以其独特的传输性质对克服电互连产生的问题有较好的针对性。本文介绍了几种光学互连方式以及采用光互连方式的光电子多芯片组件。     

ULSI互连系统热特性的模拟

应用基于有限元算法的软件ANSYS对0.15μm工艺条件下的一个ULSI电路的五层金属互连结构进行了热特性模拟和分析．模拟了这个经多目标电特性优化了的互连结构在采用不同金属(Cu或Al)互连线及不同电介质(SiO2或低介电常数材料xerogel)填充条件下的热分布情况,计算了这些条件下此互连结构的温度分布．并将结果与Stanford大学模拟的另一种五层金属布线结构的热特性结果进行了比较．讨论了低介电常数材料的采用对于互连结构散热情况的影响．此外,还简要地介绍了ANSYS的性能和用于热模拟的原理和特色．     

低k层间介质研究进展

介绍了低k介质材料的研究和发展状况,从制备方法和材料特性等不同角度对低k材料进行分类,并结合ULSI对低k材料的要求讨论了低k材料在ULSI中的应用前景。     

用于钴互连CMP抛光液的研究进展

当集成电路技术节点进入10 nm及以下，传统的铜(Cu)互连材料面临着阻容(RC)延迟高、电子散射强等问题，钴(Co)作为制程工艺中的新材料，以其更低的电阻率、更高的硬度和更低的平均电子自由程，成为了替代Cu作为互连材料的优选金属。化学机械抛光(CMP)是去除Co布线层多余材料，实现全局平坦化的唯一技术。而抛光液作为CMP工艺中最重要的耗材之一，其性能的好坏直接决定了晶圆的抛光效果和良品率。回顾了近年来钴互连金属材料的各种新型抛光液的国内外研究进展，讨论了不同化学添加剂对Co材料的去除速率、腐蚀抑制和表面质量的影响。同时总结了钴互连CMP抛光液面临的挑战及发展方向。     

铜互连CMP碟形缺陷及铜残留的研究

随着器件的特征尺寸越来越小,集成良越来越高,超大规模集成电路（ULSI）中设计的金属导线变细使得金属电阻增大,产生的热量增多,从而产生了严重的电迁移现象,同时由于线间电容和金属电阻增大引起的延迟（RC Delay）也不断恶化,这些都大大影响了器件的性能。传统的铝互连工艺因不能满足器件要求也逐渐被铜互连工艺取代。     

面阵列CSP仿真的可靠性预测

随着SMT技术的发展，集成电路封装互连，尤其是球栅阵列和面阵列CSO的互连可靠性成为人们关注的重点。其关系到这些互连技术的推广应用。本通过一系列的模拟实验，获取一些关键数据，从而开发出分析IC封装互连可靠性的新方法。并采用SRS软件作为预测可靠性的工具。创建和分析IC封装互连的新方法可为当今高性能产品提供可靠的需求。具有球栅阵列(BGA)特征的较新型的元件封装与面阵列互连组合形成了一类应用技术，这种技术能够容纳更多引线数，占用的板子空间小，而且还实现了宽间隙下的互连。对面阵列引线性能的调研已成为人们密切关注的领域，并对此展开了一系列的研究。必须考虑为下一代封装开发可靠的、低应力互连的方法。由于BGA不同于传统的组装方法，不存在将柔性引线弯曲连接的工艺步骤，显然，迫切期望为面阵列封装开发依附引线。因此，而为新BGA在开发一类小型化的IC封装以满足这种迫切需求。我们将其统称为芯片级封装(CSP)。已开发出这些小型化封装可使许多与倒装芯片技术相关的性能优势尽可能地满足广大用户的要求，而不需要用户来处理和组装未被保护的裸芯片。为获得引线柔性或释放应力，需要采用一种综合策略。首先，有必要说明可能会影响现代焊接的组件的合理应用的许多设计特性。     

多层空气隙Cu互连结构耦合电容的优化

随着超大规模集成电路特征尺寸不断缩小,多层cu互连之间的RC延迟成为一个越来越严重的问题.由于低介电常数(low-k)材料配合空气隙(air gap)结构可用于降低Cu互连导线间的耦合电容从而改善RC延迟特性,建立了单层和多层空气隙Cu互连结构的有限元分析模型,以研究空气隙结构尺寸与互连介质等效介电常数的关系.结果表明,在单层空气隙Cu互连结构中,通过增加互连导线间空气隙的结构尺寸可以减小Cu互连结构中的耦合电容,进而改善RC延迟特性;在多层空气隙Cu互连结构中,通过改变IMD和ILD中空气隙的尺寸结构可以得到RC延迟性能优化的多层空气隙Cu互连结构.     

基于45 nm技术的ULSI互连结构的温度模拟

应用自行建立的准二维简化模型，计算了三种基于45nm节点技术的ULSI九层低介电常数介质互连结构的温度升高。与ANSYS的分析对比表明，简化模型误差为7．7％。三种互连结构中，结构Ⅲ设计具有最佳的散热能力，不仅工作时绝对温升小，而且随衬底温度和介质导热系数的温升加大也小；结构Ⅰ的散热能力良好，结构Ⅲ最差。对三种互连结构的尺寸分析表明，层间介质的厚度对互连系统的温升影响大，必须在电学模拟和温度模拟完成后找到一个最佳厚度值，以保证既有好的散热条件，又有利于减小RC延迟。互连结构的温升随电介质导热系数的减小呈二阶指数升高，特别当介质导热系数小于0．1W／℃·m时，互连结构设计将会成为器件温升和系统可靠性的关键所在，引入新技术或许势在必行。     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.     

High-performance germanium-seeded laterally crystallized TFTs forvertical device integration

Increasing chip complexity and area has resulted in interconnect delay becoming a significant fraction of overall chip delay. Continued scaling of design rules will further aggravate this problem. Vertical integration of devices will enable a substantial reduction in chip size and thus in interconnect delay. We present a novel technique to achieve vertical integration of CMOS devices. Germanium is used as a seeding agent at the source and/or drain of thin film transistors (TFTs) to laterally crystallize amorphous silicon films, resulting in high-performance devices. This is achieved through the formation of large grain polysilicon with a precise control over the location of the grain. TFTs have been demonstrated offering substantial performance improvement over conventional unseeded polycrystalline TFTs, with demonstrated mobilities as high as 300 cm2/V-s. The process is fully CMOS compatible and has a low thermal budget. It is highly scalable to deep-submicron technologies and, with suitable optimization, should enable the production of high-performance, high density, vertically integrated ULSI     

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area     

On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance

Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rho_Cu), is an important performance metric for back-end-of-line (BEOL) process assessment. As process technology scales, interpretation of fundamental process-induced RC delay variations becomes a challenge as the relative importance of statistical process-induced fluctuations (variation of critical dimensions during plasma etching of low-k materials, line profiles, thickness nonuniformity, etc.) grows rapidly and begins to show. A more accurate interpretation of experimental data and prediction of future performance trends requires a more realistic assessment that accounts for such statistical fluctuations. In this paper, an inventory of the most common possible sources of statistical process-induced RC delay variations is made, parameterized, and subsequently used to generate a realistic 2-D interconnect model from which, R and C, and thereby RC delay, are computed. For both wire resistivity and RC, response surface models (RSM) are subsequently generated based on the results of a full factorial design-of-experiment analysis with these input parameters. Finally, based on the RSMs, an improved methodology of interconnect performance evaluation is proposed.     

Stochastic interconnect modeling, power trends, and performancecharacterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D     

Tradeoff between interconnect capacitance and RC delay variationsinduced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed     

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.