Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

In this paper, a novel method of fabricating three–dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.     

Microfabricated Silicon High-Frequency Waveguide Couplers and Antennas

A method has been developed to fabricate waveguide-to-waveguide couplers and tapered dielectric rod antennas for the millimeter-wave regime from microetched silicon. A proof-of-concept study shows that the structures can be realized using relatively simple wet etching and robotic process control. Experimental measurements of the waveguide-waveguide couplers agree in key features with simulations. The results indicate that two-stepped tapers perform nearly as well as smooth linear tapers, but are much easier to fabricate. Coupling transmissivity of better than -1 dB, and peak antenna gain of 8-10 dB are indicated at W-band frequencies. Lateral dimension etch control of 5-mum precision was realized. To solve a challenge of controlling the length of the first step, either an improved masking method or a switch to dry etching processes is required.     

Ultralow Temperature Processing and Integration of Dielectric Resonators on Silicon Substrates for System-on-Chip Applications

Ultralow temperature processing of Ba₂Ti₉O₂₀ thin-film ceramics and the attachment of a porous dielectric resonator cylinder on a conducting prepatterned silicon substrate have been accomplished using a hydrothermal process at 150degC/3 h. Enhanced densification and mechanical strength at the bulk ceramic-thin-film interface were induced by a dissolution-crystallization process involving a sol-gel solution under 13-15 atm pressure. Recrystallization forms electrical bridges between powder particles to form an interconnected microstructure, which eliminates grain boundary defects and, hence, improves the dielectric properties. This method has potential for growth of dielectric resonators on integrated circuits for system-on-chip applications and is implemented for the fabrication of an integrated dielectric resonator antenna.     

Dielectric Resonator Antenna on Silicon Substrate for System On-Chip Applications

This paper presents for the first time the design and performance of a novel integrated dielectric resonator antenna fabricated on a high conducting silicon substrate for system on-chip applications. A differential launcher to excite the ${rm TE}_{01delta}$ mode of the high permittivity cylindrical dielectric resonator was fabricated using the IBM SiGeHP5 process. The proposed antenna integrated on a silicon substrate of conductivity 7.41 S/m has an impedance bandwidth of 2725 MHz at 27.78 GHz, while the achieved gain and radiation efficiency are 1 dBi and 45% respectively. The design parameters were optimized employing Ansoft HFSS simulation software. Very good agreement has been observed between simulation and experimental results. The results demonstrate that integration of dielectric resonator antennas on silicon is viable, leading to the fabrication of high efficient RF circuits, ultra miniaturization of ICs and for the possible integration of active devices.      

无压力辅助硅/玻璃激光局部键合

提出了一种新的无需外压力作用的硅/玻璃激光局部键合方法,通过对晶圆进行表面活化处理,选择合适的激光参数及加工环境,成功地实现了无压力辅助硅/玻璃激光键合.同时研究了该键合工艺参数如激光功率、激光扫描速度、底板材料等的影响.实验表明,激光功率越大,扫描速度越小,键合线的宽度就越大.实验结果显示,该方法能有效减少键合片的残余应力,控制键合线宽,并能得到较好的键合强度.该工艺可为MEMS器件的封装与制造提供简洁、快速、键合区可选择的新型键合方法.     

High Performance Inductors on CMOS-Grade Trenched Silicon Substrate

This paper reports on a new implementation of high-quality factor copper inductors on CMOS-grade silicon substrates (p = 10-20 Omega ldr cm) using a CMOS-compatible process. A low-temperature fabrication sequence (<300degC) is used to reduce the loss in silicon at RF frequencies by trenching the silicon substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss dielectric to close the open areas and create a rigid low-loss island, referred to as Trenched Si Island. This method does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. A one-turn 0.8 nH inductor fabricated on a Trenched Silicon Island exhibits a very high peak quality factor of 71 at 8.75 GHz with a self-resonant frequency larger than 15 GHz.     

以BCB为介电材料的硅基集成微带贴片天线的制备

This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene(BCB) dielectric.The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer,and is fully compatible with the microwave multi-chip module packaging process.Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna.The as-fabricated antenna is characterized,and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.     

硅微机械电子隧穿红外探测器

介绍了一种新型的非制冷高灵敏度硅微机械电子隧穿红外探测器的工作原理 ,详细描述了这种红外探测器的设计思想和制作工艺 ,采用微机械体硅加工的三层硅结构制作出探测器原理样品 ,通过和反馈电路 (包括前置放大电路 )连接测试表明 :电子隧穿位移传感器部分的分辨率可达 10 -4 nm/ Hz,红外探测器样品已能敏感红外信号。     

Fabrication of thick silicon nitride blocks for integration of RF devices

A fabrication process for the creation of thick (tens of micrometres) silicon nitride blocks embedded in silicon wafers has been developed. This new technology allows the use of silicon nitride as dielectric material for radio frequency (RF) circuits on standard CMOS-grade silicon wafers. Measurement results show that a performance similar to that of dedicated glass substrates can be reached     

High-temperature, low-modulus adhesive attach for large-areathin-film processing on silicon and alumina tiles

The fabrication of high-density interconnect structures typically involves sequential processing of alternate layers of thin organic dielectric materials and conducting copper lines. With the continued push toward low-cost fabrication, large-area processing of thin-film materials is being aggressively pursued by the electronic packaging industry. The objective of the ongoing work at Georgia Tech is to develop innovative materials, models, and processing techniques to facilitate large-area processing of alumina and silicon tiles. As the alumina and silicon tiles are commercially available in smaller dimensions, a palletization approach has been developed to facilitate large-area processing. In the palletization approach, alumina and silicon tiles are attached to re-usable glass pallets with an in-house developed thermally-stable, reworkable, and highly-compliant adhesive     

Silicon high-resistivity-substrate millimeter-wave technology

The application of molecular beam epitaxy (MBE) and X-ray lithography for the fabrication of monolithic integrated millimeter-wave devices on high-resistivity silicon has been investigated. Process compatibility and the retention of high-resistivity characteristics were measured using the spreading resistance method and Hall measurements after various process steps. Microstrip resonators of ring and linear geometry were fabricated on 10 000 Ω.cm silicon substrates. For linear microstrip resonators, the attenuation was found to be less than 0.6 dB/cm at 90 GHz. A 95-GHz IMPATT oscillator circuit and a planar microstrip antenna array have been fabricated on highly insulating silicon substrates. For the oscillator, a combined monolithic-hybrid integration technique was used to attach the discrete IMPATT diode to the resonator circuit. The oscillator does not require tuning elements. Preliminary experimental results are 8 mW of output power with 0.2 percent efficiency at 95 GHz.     

Silicon nitride thin-film deposition by LPCVD with in situ HF vaporcleaning and its application to stacked DRAM capacitor fabrication

Silicon nitride film deposited by LPCVD with newly developed in situ HF vapor cleaning has been studied and applied to fabricate dielectric films for stacked DRAM capacitors. Using this method, an oxide-free surface of underlaid poly-Si can be obtained. Silicon nitride film deposited on this surface has been verified by FTIR measurement to have the stoichiometrically proper composition of Si₃N₄ . However, the film was found to be selectively deposited on poly-Si electrodes. This selective deposition degrades the reliability of the stacked capacitor, because the silicon nitride can not completely cover the periphery of poly-Si electrodes on SiO₂. We propose a simple process that avoids the problem making it possible to apply silicon nitride film to stacked-capacitor fabrication. Stacked capacitors fabricated by this process exhibit very low leakage current and high electrical reliability even for ultra-thin silicon nitride films less than 5 nm thick     

二维硅微机械陀螺的研究

报道了一种依靠载体的旋转作为驱动,能敏感载体偏航角速度与自转角速度的二维硅微机械陀螺的原理、硅摆制作、敏感元件封装和检测。分别用仿真器和速率转台对其二维特性进行测试,结果证实该硅微机械陀螺能够敏感旋转载体的偏航和旋转体自身的角速度,比例系数随旋转角速度增加而增加。陀螺性能测试说明这种陀螺达到中等精度的使用要求。     

Design of a Silicon Based High Speed Plasmonic Modulator

In this paper, we propose a silicon-based high-speed plasmonic modulator. The modulator has a double-layer structure with a 16 μm long metal-dielectric-metal plasmonic waveguide at the upper layer and two silicon single-mode waveguides at the bottom layer. The upper-layer plasmonic waveguide acts as a phase shifter and has a dielectric slot that is 30 nm wide. Two taper structures that have gradually varied widths are introduced at the bottom layer to convert the photonic mode into plasmonic-slot mode with improved coupling efficiency. For a modulator with two 1 μm-long mode couplers, simulation shows that there is an insertion loss of less than 11 dB and a half-wave voltage of 3.65 V. The modulation bandwidth of the proposed modulator can be more than 100 GHz without the carrier effect being a limiting factor in silicon. The fabrication process is also discussed, and the proposed design is shown to be feasible with a hybrid of CMOS and polymer technology.     

An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

An integrated process modeling methodology using a coupled cure-thermal-stress analysis approach has been developed to determine the evolution of warpage and stresses during the sequential fabrication of high-density electronic packaging structures. The process modeling methodology has been demonstrated, for example, with a bi-layer structure consisting of a 3 mil (76.2 /spl mu/m) thick Vialux 81 photo-definable dry film (PDDF) polymer on a silicon substrate. Extensive material characterization of the thermo-mechanical properties of the thin film polymer is presented, including the development of a viscoelastic material model. The predicted warpage values have been validated with shadow Moire experiments, while the predicted stress values have been validated with experimental data using the Flexus Thin Film Stress Measurement Apparatus. Good agreement is seen between the predicted and the experimental warpage and stress values during the entire cure cycle. Finally, the importance of incorporating viscoelastic polymer behavior and processing history is emphasized in the context of developing the multi-layered high-density wiring integrated substrate fabrication process.     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

Polymer Electronics Systems - Polytronics

Current trends in the development of electronics systems show that the provision of thin flexible components and semiconductors plays a decisive role in the steadily progressing development of highly integrated systems. A new generation of thin flexible electronic systems arises. At Fraunhofer IZM, inline manufacturing processes for polymer electronic systems are developed on production type equipment. A low-cost process for the fabrication of polymer electronics has been developed performed completely on continuous flexible foil substrates with typical thickness of 50 /spl mu/m, enabling low-functional electronic circuit fabrication with IC complexity up to 30 devices at present (2005). This process opens further possibilities to integrate thin silicon circuits and plastic microelectromechanical systems (MEMS) structures in the same fabrication and process environment. Microsystems incorporating fluidic, mechanical, optical, and electrical components are under research and development at present. Key applications scenarios for the polymer electronics predict fully applicable displays, embedded MEMS, labels for broad-band wireless communication, polymer batteries, and photovoltaic cells.