CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.     

A Ku band internally matched high power GaN HEMT amplifier with over 30%of PAE

正We report a high power Ku band internally matched power amplifier(IMPA) with high power added efficiency(PAE) using 0.3μm AlGaN/GaN high electron mobility transistors(HEMTs) on 6H-SiC substrate.The internal matching circuit is designed to achieve high power output for the developed devices with a gate width of 4 mm.To improve the bandwidth of the amplifier,a T type pre-matching network is used at the input and output circuits,respectively.After optimization by a three-dimensional electromagnetic(3D-EM) simulator,the amplifier demonstrates a maximum output power of 42.5 dBm(17.8 W),PAE of 30%to 36.4%and linear gain of 7 to 9.3 dB over 13.8-14.3 GHz under a 10%duty cycle pulse condition when operated at V_(ds) = 30 V and V_(gs)=—4 V.At such a power level and PAE,the amplifier exhibits a power density of 4.45 W/mm.     

High Power SiGe X-Band (8～10GHz) Heterojunction Bipolar Transistors and Amplifiers

Limited by increased parasitics and thermal effects as device size increases,current commercial SiGe power HBTs are difficult to operate at X-band (8～12GHz) frequencies with adequate power added efficiencies at high power levels.We find that,by changing the heterostructure and doping profile of SiGe HBTs,their power gain can be significantly improved without resorting to substantial lateral scaling.Furthermore,employing a common-base configuration with a proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs,thus permitting these devices to be efficiently operated at X-band frequencies.In this paper,we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8～10GHz.At 10GHz,a 22.5dBm (178mW) RF output power with a concurrent gain of 7.32dB is measured at the peak power-added efficiency of 20.0%,and a maximum RF output power of 24.0dBm (250mW) is achieved from a 20 emitter finger SiGe power HBT.The demonstration of a single-stage X-band medium-power linear MMIC power amplifier is also realized at 8GHz.Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components,a linear gain of 9.7dB,a maximum output power of 23.4dBm,and peak power added efficiency of 16% are achieved from the power amplifier.The MMIC exhibits very low distortion with 3rd order intermodulation (IM) suppression C/I of -13dBc at an output power of 21.2dBm and over 20dBm 3rd order output intercept point (OIP3).     

垂直腔面发射激光器

The development and application of vertical-cavity surface-emitting lasers (VCSELs) are summarized in this paper. The emphasis is focused on the high power single and 2-D arrays bottom-emitting VCSELs with a wavelength of 980nm. A distinguished device performance is achieved. The maximum continuous-wave (CW) output power of large aperture single devices with active diameters up to 500μm is as high as 1.95W at room temperature, which is to our knowledge the highest value reported for a single device. Size dependence of the output power, the threshold current and the differential resistance are discussed. A 16 elements array with 200μm aperture size (250μm center spacing) of individual elements shows a CW output power of 1.32W at room temperature.     

输出功率-3dBm的射频发射前端在802.11g中的应用

A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is -3 dBm while the corresponding EVM is -27 dB which is necessary for the 802.1 1g standard of EVM at-25 dB. With the adopted gain control strategy the output power changes from -14.3 to -3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.     

A 4–9 GHz 10W wideband power amplifier

A 4-9 GHz wideband high power amplifier is designed and fabricated, which has demonstrated saturated output power of 10 W covering 6-8 GHz band, and above 6 W over the other band. This PA module uses a balance configuration, and presents power gain of 7.3 ＋ 0.9 dB over the whole 4-9 GHz band and 39% power-added efficiency （PAE） at 8 GHz. Both the input and output VSWR are also excellent, which are bellow -10 dB.     

A Ka-band 22 dBm GaN amplifier MMIC

A Ka-band GaN amplifier MMIC has been designed in CPW technology,and fabricated with a domestic GaN epitaxial wafer and process.This is,to the best of our knowledge,the first demonstration of domestic Kaband GaN amplifier MMICs.The single stage CPW MMIC utilizes an AlGaN/GaN HEMT with a gate-length of 0.25μm and a gate-width of 2×75μm.Under V_ds=10 V,continuous-wave operating conditions,the amplifier has a 1.5 GHz operating bandwidth.It exhibits a linear gain of 6.3 dB,a maximum output power of 22 dBm and a peak PAE of 9.5%at 26.5 GHz.The output power density of the AlGaN/GaN HEMT in the MMIC reaches 1 W/mm at Ka-band under the condition of V_ds=10 V.     

X 波段氮化镓合成固态放大器

Based on a self-developed A1GaN/GaN HEMT with 2.5 mm gate width technology on a SiC substrate, an X-band GaN combined solid-state power amplifier module is fabricated. The module consists of an AIGaN/GaN HEMT, Wilkinson power couplers, DC-bias circuit and microstrip line. For each amplifier, we use a bipolar DC power source. Special RC networks at the input and output and a resistor between the DC power source and the gate of the transistor at the input are used for cancellation of self-oscillation and crosstalk of low-frequency of each amplifier. At the same time, branches of length 3λ/4 for Wilkinson power couplers are designed for the elimination of self-oscillation of the two amplifiers. Microstrip stub lines are used for input matching and output matching. Under Vds = 27 V, Vgs = -4.0 V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5.6 dB with power added efficiency of 23.4%, and output power of 41.46 dBm （14 W）, and the power gain compression is 3 dB. Between 8 and 8.5 GHz, the variation of output power is less than 1.5 dB.     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier（PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter.The third harmonic of the power stage and driver stage can be cancelled out in a specific power region.The two-stage PA fabricated in a standard 0.18μm CMOS process delivers 27.5 dBm with 27%PAE at the 1-dB compression point(P_1dB) and offers 21 dB gain.The PA achieves 5.5%EVM and meets the spectrum mask at 20.5 dBm average power.Another conventional PA with a zero-cross-point of g_m3 bias is also fabricated and compared to prove its good linearity and efficiency.     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

Design challenges of a fully integrated 65 nm CMOS half cascode SFDS PA

This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB at 2.2 GHz with a bandwidth at −3 dB (B _w -3 dB) of 43%. At 1.95 GHz, the maximal output power (P _max ) is 23.3 dBm with a power added efficiency (PAE) of 12%. The output power at 1 dB compression (OCP ₁ ) is 21 dBm. At 2.4 GHz, Pmax is 23 dBm with a PAE of 11.3%. At this frequency, the OCP1 is 20 dBm.     

New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S₂₁) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S₂₁ is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P_sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP_1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.     

基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

1–8 GHz high efficiency single-stage travelling wave power amplifier

This paper describes a Class-A/AB wideband power amplifier that comprises of a single-stage transistor travelling wave structure in which capacitive coupling and frequency dependent lossy artificial-line are employed at the input of the active device. The proposed technique significantly enhances the amplifier’s gain-bandwidth product, input match and gain flatness performance. To ensure the amplifier delivers a predefined power to the load over its entire operating band 2-to-8 GHz a broadband load-pull technique was applied at the output of the amplifier. To avoid reduction in the amplifier’s bandwidth resulting from parasitic capacitive effects associated with the off-chip choke inductor a wideband RF choke was designed. The 1.31 × 2.93 mm² power amplifier was fabricated using 0.25 μm GaAs pHEMT MMIC process. The measurement results show that the proposed amplifier delivers an average P _sat of 29.5 dBm and P _out,1 dB of 26 dBm, and the corresponding PAE levels are 55 and 35 % for the P _sat and P _out,1 dB, respectively.     

Analysis and design of high-power and efficient,millimeter-wave power amplifier systems using zero degree combiners

We present the analysis and design of high-power millimetre-wave power amplifier (PA) systems using zero-degree combiners (ZDCs). The methodology presented optimises the PA device sizing and the number of combined unit PAs based on device load pull simulations, driver power consumption analysis and loss analysis of the ZDC. Our analysis shows that an optimal number of N-way combined unit PAs leads to the highest power-added efficiency (PAE) for a given output power. To illustrate our design methodology, we designed a 1-W PA system at 45 GHz using a 45 nm silicon-on-insulator process and showed that an 8-way combined PA has the highest PAE that yields simulated output power of 30.6 dBm and 31% peak PAE.     

A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE

A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P_1 dB of 23.2 dBm and a P_SAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors.     

1 W Ku-band AlGaAs/GaAs power HBT's with 72% peak power-addedefficiency

High power and high-efficiency multi-finger heterojunction bipolar transistors (HBT's) have been successfully realized at Ku-band by using an optimum emitter ballasting resistor and a plated heat sink (PHS) structure. Output power of 1 W with power-added efficiency (PAE) of 72% at 12 GHz has been achieved from a 10-finger HBT with the total emitter size of 300 μm². 72% PAE with the output power density of 5.0 W/mm is the best performance ever reported for solid-state power devices with output powers more than 1 W at Ku-band     

Design of power-controlled class1 Bluetooth CMOS power amplifier

In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the f_t and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.     

A Ka-band low power consumption MMIC core chip for T/R modules

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P_1dB of –3 dBm. In the transmitting mode, the gain and output P_1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.