Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

New solutions for intermetal dielectrics using trimethylsilane-based PECVD processes

Trimethylsilane, (CH₃)₃SiH, is a non-pyrophoric organosilicon gas. This material is easily used to deposit dielectric thin films in standard PECVD systems designed for SiH₄. In addition to deposition of standard dielectrics (e.g. SiO₂), trimethylsilane can be used to deposit reduced permittivity (low-k) dielectric versions of amorphous hydrogenated silicon carbide and its oxides. The low-k carbides (k<5.5) are highly insulating and useful as hard masks, etch stops and copper diffusion barriers. The low-k oxides (2.6<k<3.0) are useful as intermetal dielectrics, and exhibit stability and electrical properties which can meet many specifications in device fabrication that are now placed on SiO₂. This paper reviews PECVD processing using trimethylsilane. Examples will show that the 3MS-based dielectrics can be used in place of SiH₄-based oxides and nitrides in advanced device multilevel metal interconnection schemes to provide improved circuit performance.     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Deposition of uniform Zr-Sn-Ti-O films by on-axis reactivesputtering

We describe the deposition of amorphous Zr-Sn-Ti-O (aZTT) dielectric thin films using conventional on-axis reactive sputtering. Thin films of composition Zr_0.2Sn_0.2Ti_0.6 O₂ have excellent dielectric properties: 40-50-nm thick films with a dielectric constant of 50-70 were obtained, depending on the processing conditions, yielding a specific capacitance of 9-17 fF/μm². Breakdown fields were measured to be 3-5 MV/cm, yielding a figure of merit εε₀E_br=15-30 μC/cm², up to eightfold higher than conventional deposited SiO₂. Leakage currents, measured at 1.0 MV/cm, were in the range 10^-9-10^-7 A/cm². This material appears well-suited for use in Si-IC device technology, for example as storage capacitors in DRAM     

A photo-oxidation generated low-k dielectric film deposited by reactive evaporation of SiO

A non-stoichiometric silicon oxide film has been deposited by evaporating SiO as a source material in Ar and O₂ mixed gas. The film is composed of SiO and SiO₂, and has a porous structure. The SiO₂ results from some part of SiO reacting with O₂ and its amount depends on the pressure in the chamber. The residual SiO in the film can be photo-oxidized into SiO₂ by ultraviolet radiation with a Hg lamp. The dielectric constant of the film after photo-oxidation is 1.89±0.04 (at frequency of 1 MHz), which shows that this porous structure film is promising for potential application as a low-k dielectric.     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

Effects of growth temperature on TDDB characteristics of N2O-grown oxides

Effects of oxide growth temperature on time-dependent dielectric breakdown (TDDB) characteristics of thin (115 Å) N₂O-grown oxides are investigated and compared with those for conventional O₂-grown SiO₂ films with identical thickness. Results show that TDDB characteristics of N₂O oxides are strongly dependent on the growth temperature and, unlike conventional SiO₂, TDDB properties are much degraded for N ₂O oxides with an increase in growth temperature. Large undulations at the Si/SiO₂ interface, caused by locally retarded oxide growth due to interfacial nitrogen, are suggested as a likely cause of degradation of TDDB characteristics in N₂O oxides grown at higher temperatures     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Dielectric breakdown mechanism of thin-SiO2 studied bythe post-breakdown resistance statistics

The dielectric breakdown mechanism of SiO₂ has been discussed on the basis of the experimental results of the post-breakdown resistance (R_bd) distribution. We have noticed for the first time that R_bd of SiO₂ in MOS devices is strongly related to the SiO₂ breakdown characteristics such as the polarity dependence or the oxide field dependence of Q_bd. In this paper, we discuss the dielectric breakdown mechanism of SiO₂ from the viewpoint of the statistical correlation between the R _bd distribution, the Q_bd. distribution, and the emission energy just at the SiO₂ breakdown, by changing the stress polarity, stress field, and the oxide thickness. For complete dielectric breakdown, it has been clarified that the R_bd distribution under the substrate electron injection is clearly different from that under the gate electron injection. We have also found that, irrespective of the stress current density, the gate oxide thickness and the stressing polarity, R_bd can be uniquely expressed by the energy dissipation at the occurrence of dielectric breakdown of SiO₂ for the complete breakdown. Furthermore, it has been clarified that R_bd does not depend on the energy dissipation at the occurrence of quasidielectric breakdown     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

Electron and hole traps in SiO2 films thermally grown onSi substrates in ultra-dry oxygen

The densities of electron and hole traps in SiO₂ films, thermally grown on Si substrates in ultra-dry oxygen, were compared with those in SiO₂ films grown in pyrogenic steam (wet-oxide films). The results show that ultra-dry-oxide films have an undetectable density of electron traps that is less that 10¹¹/cm² , and little interface-states generation during carrier injection. However, hole traps in ultra-dry-oxide films are high, (2.6±0.1)×10¹²/cm² compared with (1.3±0.2)×10¹²/cm² in wet-oxide films, and these increase by a factor of two with post-oxidation anneal in ultra-dry Ar. The results of electron spin resonance measurements of E' centers in SiO₂ films are consistent with the results of electrical measurements. These suggest that there is a tradeoff correlation between the density of electron traps and hole traps, with respect to the amount of water- or hydrogen-related defects in SiO₂     

Enhanced injection in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications: experiment

In this paper, n⁺⁺-poly/SiO_x/SiO₂/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiO_x films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiO_x film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n⁺⁺ -poly/SiO_x/SiO₂/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiO_x films is proposed. In SiO_x films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiO_x/SiO₂ interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiO_x films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap