Bluetooth ASIC及其嵌入式应用

介绍了bluetooth ASIC内部结构、特性以及接口逻辑和嵌入式应用设计实例.由bluetooth基带控制器与无线射频收发器接口组成的bluetooth模块,通过UART/PCM和USB向数字和语音设备提供全兼容的bluetooth接口,可方便地构成bluetooth设备.     

一种基于DSP的人工耳蜗语音处理器设计

传统的人工耳蜗语音处理器采用ASIC设计,投入成本高,可移植性差,设计了一种基于TMS320VC5509A的人工耳蜗语音处理器。该处理器采用双麦克风接受语音信号,实现了语音信号的自适应噪声消除和CIS(Continuous Interleaved Sampling)方案。同一段语音由DSP采样处理得到的刺激脉冲与MATLAB采样处理的结果基本相同。实验结果表明,基于DSP的人工耳蜗语音处理器能实现语音信号中噪声的消除并得到良好的刺激脉冲。     

ASIC设计流程和方法

ASIC的复杂性不断提高,同时工艺在不断地改进,如何在较短的时间内开发一个稳定的可重用的ASIC芯片的设计,并且一次性流片成功,这需要一个成熟的ASIC的设计方法和开发流程.本文结合NCverilog,DesignCompile,Astro等ASIC设计所用到的EDA软件,从工艺独立性、系统的稳定性、复杂性的角度对比各种ASIC的设计方法,介绍了在编码设计、综合设计、静态时序分析和时序仿真等阶段经常忽视的问题以及避免的办法,从而使得整个设计具有可控性.     

平台FPGA的发展带来了什么?

当今多平台FPGA动摇ASIC/ASSP供应商. 有关FPGA是否是ASIC和ASSP可行替代品的争论已经持续了近十年.iSuppli、GartnerDataquest及其它业界分析师的研究表明当前正处在ASIC设计新客户不断减少,FPGA设计新客户不断增多的趋势当中.     

Rapid Chip设计平台快速设计系统级芯片

引言 Rapidchip Platform ASIC基本上是在一个芯片(SoC)上快速设计系统而提供的新方法.这些耐用的PlatformASIC填补了FPGA和标准单元ASIC之间的空隙,并组合了两者最好的特性.RapidchipPlatform ASIC探讨交付包含复杂的嵌入式IP的高性能和高密度的解决方案;并且它们比标准单元ASIC要少一半的设计时间,开发成本是几分之一.     

FPGA成为替代ASIC的最佳选择

多年来,Xilinx公司的可编程逻辑技术始终扮演着ASIC替代解决方案的角色.过去十多年来,每次当ASIC技术实现摩尔定律的预期,Xilinx FPGA和CPLD都迅速填补了由此而留下的间隙.最近,有些ASIC制造商推出了称为结构化ASIC(Structured ASIC)的改进ASIC结构,试图解决与基于标准单元的ASIC和门阵列相关的一些问题.但最终,人们都会问到这一决定性问题,"如果我们需要100万门至500万门的设计,到底哪种技术最佳地结合了硬件、软件和设计支持,从而可最好地满足我们的需要?"     

ASIC设计技术及其发展研究

对ASIC设计的工作流程和相关工具软件进行了简要介绍,并概括了ASIC设计的发展过程和较新趋势,以促进大家对芯片设计领域的认识和了解.     

借力HardCopy兼得鱼和熊掌——记Altera?结构化ASIC HardCopy?解决方案

本文以Altera公司结构化ASIC解决方案HardCopy为例,对结构化ASIC的市场和发展趋势进行了分析,同时对结构化ASIC的技术、设计流程和优势进行了详细的分析.     

ASIC的设计方法和设计工具（上）

80年代以来,ASIC技术发展迅速,它是集成电路设计自动化、规范化以及制造工艺标准化的标志。ASIC的出现日益改变着电子产品的面貌,促进了微电子产业的革新。文章讲述了ASIC的设计方法和设计过程以及整机中应用ASIC的优越性,介绍了ASIC的CAD设计工具并指出ASIC设计是系统和电路工程师的新课题。     

专用集成电路设计分析

本文介绍了专用集成电路的设计方法，分别阐述了ASIC设计的分类，ASIC的高层设计语言(VHDL)，数字逻辑系统的仿真，ASIC的设计流程以及ASIC的故障分析与测试。     

An Economical Hardware Realization of a Digital Linear Predictive Speech Synthesizer

Speech analysis/synthesis algorithms utilizing linear prediction coefficients have certain advantages over those employing formantbased techniques. For example, 4-kHz speech samples may be synthesized using a basic sequence of 10 multiply/adds followed by a single addition of the current sample of the excitation function. Real-time software synthesis of 4-kHz speech is possible (using this technique) on certain 16-b minicomputers, but the central processing unit (CPU) overhead may approach 100 percent. We describe an economical (< 600-dollar) hardware realization of a 4-kHz digital linear predictive speech synthesizer which requires, at most, a CPU overhead of about 40 percent real time. The device is constructed of standard TTL/MOS logic and consists (essentially) of a high speed 2's complement multiplier/adder capable of calculating a 26-b product (10-b speech samples, 16-b coefficients) in 0.33 μs, and a dual shift register. In addition, a procedure is discussed which enables the device to be used both as a formant synthesizer for vowels or voiced consonant production, and as a predictive synthesizer for other speech sounds. This procedure, hybrid synthesis, permits the utilization of formant concatenation techniques and reduces the coefficient storage required to specify vowels/voiced consonants by about 60 percent.     

A Low-Rate Digital Formant Vocoder

A complete algorithm of a 1200-bits/s digital formant vocoder system is described. This vocoder algorithm draws heavily on the results of recent research in linear predictive coding. The transmitting parameters are frequencies and amplitudes of the first three formants, the pitch period, voiced/unvoiced decision, and the gain. Formant bandwidths are estimated at the synthesizer by using the amplitude information. The synthesizer structure is in the parallel form. The synthetic speech quality at 1200 bits/s is reasonably good; most of the speech is intelligible and speaker-recognizable.     

A 3 /spl mu/m NMOS high-performance LPC speech synthesizer chip

A high performance speech processing integrated circuit (SPIC) based on linear predictive coding (LPC) techniques is presented. Both system and technological aspects of the SPCI design are covered in detail. The SPIC synthesizer chip will normally be used in a three-chip minimum system configuration including the synthesizer, a microcomputer, and an external vocabulary ROM. The speech quality can be tailored to the user's requirements by varying the bit rate between the vocabulary ROM and the microcomputer from 1.1 to 8.5 kbit/s. Among the specific features of the SPIC are pitch synchronous synthesis, speech parameters interpolation capability, silence, and power-down mode. Moreover, the digital filter output is interpolated at a high sampling rate (32 kHz) to avoid the necessity for off-chip filtering. An 8-bit PCM output (A law) and a 16-bit linear-coded output are provided. The SPIC can be delivered in two different bonding configurations either for small system application (three-chip system) or for larger system configuration.     

A Multi-level GMM-Based Cross-Lingual Voice Conversion Using Language-Specific Mixture Weights for Polyglot Synthesis

For any given mixed-language text, a multilingual synthesizer synthesizes speech that is intelligible to human listener. However, as speech data are usually collected from native speakers to avoid foreign accent, synthesized speech shows speaker switching at language switching points. To overcome this, the multilingual speech corpus can be converted to a polyglot speech corpus using cross-lingual voice conversion, and a polyglot synthesizer can be developed. Cross-lingual voice conversion is a technique to produce utterances in target speaker’s voice from source speaker’s utterance irrespective of the language and text spoken by the source and the target speakers. Conventional voice conversion technique based on GMM tokenization suffer from degradation in speech quality as the spectrum is oversmoothed due to statistical averaging. The current work focuses on alleviating the oversmoothing effect in GMM-based voice conversion technique, using (source) language-specific mixture weights in a multi-level GMM followed by selective pole focusing in the unvoiced speech segments. The continuity between the frames of the converted speech is ensured by performing fifth-order mean filtering in the cepstral domain. For the current work, cross-lingual voice conversion is performed for four regional Indian languages and a foreign language namely, Tamil, Telugu, Malayalam, Hindi, and Indian English. The performance of the system is evaluated subjectively using ABX listening test for speaker identity and using mean opinion score for quality. Experimental results demonstrate that the proposed method effectively improves the quality and intelligibility mitigating the oversmoothing effect in the voice-converted speech. A hidden Markov model-based polyglot text-to-speech system is also developed, using this converted speech corpus, to further make the system suitable for unrestricted vocabulary.     

汉语语音合成系统中激励源和声调模型研究

在语音合成器中激励源对合成语音的质量有极为重要的作用，本文对几种浊音激励源及其合成的结果进行了分析比较，同时对激励源细动态变化特性进行了研究。汉语的声调对合成语音质量影响很大，本文通过对语音基频、音长、音强的变化分析研究，建立了汉语的声调模型。在此基础上开发了一种并联型共振峰模型，该合成器能合成出具有较好清晰度和自然度的语音     

An integrated speech synthesizer

A large scale integrated speech synthesizer is described. It is based on linear predictive coding which is a voice compression technique. The speech synthesizer is suitable for a wide range of applications, particularly in the telecommunications field. The circuit has been designed and fabricated in standard NMOS silicon-gate enhancement-depletion technology. The multidrain MOS (MDMOS) technique used permits a symbolic layout which makes the chip design remarkably simple.     

LPC语音合成器的词汇编码优化

语音合成器的合成音质主要取决于词汇表的编制.词汇表的编制主要是在计算机上用非实时软件完成.本文主要讨论编制词汇表的过程以及影响语音合成器音质的因素.     

基于六线逼近法的DDFS算法的实现

为了提高直接数字频率合成技术的资源利用率,结合三角函数的对称性和线性幅值逼近算法对正弦信号分段算法进行研究,提出基于六线线性逼近优化算法,使用6段不大于正弦值的均与分段的线段逼近之后,使用QE-ROM (量化-误差存储)存储线段与正弦值差值的办法,在不影响频率特征和最大误差特性基础上,实现了算法的简化,并压缩了误差补偿存储器所需存储空间。实验结果表明对于9 bit正弦输出只需使用336 bit存储器和4个加法器3个选择器一个比较器即可实现整个系统,并且最大的工作频率达到了210 MHz,共消耗110个LE,49个存储器。压缩比远远高于传统的压缩算法。     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...