Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10^-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO2energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.     

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm² capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d_eff, while d_eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10⁷ h, and the distribution becomes insignificant below 2 × 10⁶ h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.     

Relation between injection barrier and contact resistance in top-contact organic thin-film transistors

We theoretically investigate the carrier injection into top-contact bottom-gate organic thin film transistors. By means of a two-dimensional drift–diffusion model, we explicitly consider thermionic and tunneling injection in combination with subsequent carrier transport into the device. Based on numerical simulations with this model, we determine the contact resistance as a function of the nominal hole injection barrier height and temperature. Depending on the barrier height or the operating temperature, we find three distinct injection regimes. Our work reveals that in all three regimes self-regulating processes exist due to which the influx of current is adjusted according to the needs of the channel at the given point of operation.     

Hot electrons and holes in MOSFET's biased below the Si—SiO2interfacial barrier

This work presents an investigation of low-voltage hot carrier injection in submicrometer size MOSFET's showing that for both electrons and holes it can take place even when the maximum energy to be gained by the applied field is less than the Si-SiO2interfacial barrier height. In the case of electrons, it is also shown that the injection process, due to Auger recombination at low applied drain-to-source voltages (VDS), is well described by the lucky-electron model (LEM) as soon as VDSexceeds the threshold for this to become applicable.     

基于过渡金属氧化物薄膜为连接层的叠层有机电制发光器件的数值模型

By utilizing a two-step process to express the charge generation and separation mechanism of the transition metal oxides （TMOs） interconnector layer, a numerical model was proposed for tandem organic light emitting diodes （OLEDs） with a TMOs thin film as the interconnector layer. This model is valid not only for an n-type TMOs interconnector layer, but also for a p-type TMOs interconnector layer. Based on this model, the influences of different carrier injection barriers at the interface of the electrode/organic layer on the charge generation ability of interconnector layers were studied. In addition, the distribution characteristics of carrier concentration, electric field intensity and potential in the device under different carrier injection barriers were studied. The results show that when keeping one carrier injection barrier as a constant while increasing another carrier injection barrier, carri- ers injected into the device were gradually decreased, the carrier generation ability of the interconnector layer was gradually reduced, the electric field intensity at the interface of the organic/electrode was gradually enhanced, and the electric field distribution became nearly linear： the voltage drops in two light units gradually became the same. Meanwhile, the carrier injection ability decreased as another carrier injection barrier increased. The simulation re- sults agree with the experimental data. The obtained results can provide us with a deep understanding of the work mechanism of TMOs-based tandem OLEDs.     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

高k栅介质MOSFETs的二维阈值电压模型

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

Ensemble Monte Carlo study of interface-state generation inlow-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFETs. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-μm channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.44 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO₂ interface). These simulations demonstrate that “lucky electron” and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-μm channel lengths     

GeSiMOSFET的纵向结构对器件性能的影响

为了研究器件参数对GeSi MOSFET器件性能的影响,本文在建立一个简单的GeSi MOSFET的器件模型的基础上,对GeSi MOSFET的纵向结构进行了系统的理论分析.确定了纵向结构的CAP层厚度、沟道层载流子面密度、DELTA掺杂浓度以及量子阱阱深之间的关系,得出了阈值电压与DELTA掺杂浓度、栅氧化层厚度及CAP层厚度之间的关系,还得出了栅压与沟道载流子面密度、栅氧化层厚度及CAP层厚度之间的关系.并且在此基础上得出了一些有意义的结果.为了更细致、精确地进行分析,我们分别对GeSi PMOSFET和GeSi NMOSFET在MEDICI上做了模拟.     

Threshold and subthreshold characteristics theory for a very small buried-channel mosfet using a majority-carrier distribution model

Simple expressions of threshold and subthreshold characteristics for a very small buried-channel MOSFET is derived from a model of majority-carrier distribution along the channel. The carrier distribution is determined from the Poisson equation for a high-low junction. The basic formula for the subthreshold characteristic is derived from the majority-carrier drift-current equation. The theory is compared with the measured threshold voltages and the measured inverse semilogarithmic slopes of subthreshold current. The theoretical curves are in a reasonable agreement with experimental results. It is shown for a buried-channel MOSFET having a channel length less than 1 μm that the threshold and subthreshold characteristics change abruptly as the channel length is reduced because the majority-carrier concentration increases through the carrier diffusion from the source and drain terminals. The theoretical estimation shows that buried-channel MOSFETs will have the less short-channel effect than surface-channel MOSFETs for a small drain voltage. The theory also predicts that the buried-channel MOSFET can be scaled down in the same way as the surface-channel MOSFET.     

Charge-sheet model for silicon carbide inversion layers

The charge-sheet model for metal-oxide-semiconductor (MOS) inversion layers is extended to silicon carbide. The generalized model is based on an analytical solution of the Poisson equation for the case of incomplete ionization of dopant impurities and incorporating Fermi-Dirac statistics. The results are compared with the conventional charge-sheet model which assumes complete impurity ionization and nondegenerate statistics. It is found that, at room temperature and for gate voltages in weak and moderate inversion, the present model predicts higher inversion-layer charge density at a given gate voltage. However, the relationship between the inversion charge and the surface Fermi potential is essentially independent of the degree of impurity ionization. In strong inversion or at temperatures above ~600 K, the differences between the two models are small. A formula is given for the threshold voltage as a function of the impurity ionization energy. The effects of several different interface state energy distributions on inversion charge are investigated. It is found that a slowly-varying interface-state density has an effect on threshold voltage of a MOSFET similar to that of a fixed oxide charge, while an interface-state density that increases at least exponentially with energy has the effect of lowering the field-effect mobility and transconductance     

A new equivalent MOSFET representation of a HEMT to analyticallymodel nonlinear charge control for simulation of HEMT devices andcircuits

It is shown that, from the point of view of the behavior of the charge and position of the Two-Dimensional Electron Gas (2-DEG) as a function of gate-source and drain-source voltages, the complex High Electron Mobility Transistor (HEMT) can be regarded as a simple Buried-Channel (BC) MOSFET. Thus, the characteristics of a HEMT, namely channel charge and capacitance/transconductance as a function of gate voltage below and above threshold are akin those of a BC MOSFET. Hence, there are discrepancies in the conventional Surface Channel MOSFET-like approach to HEMT modeling. Existing simple BC MOSFET dc and ac models can be used for on-paper analysis and computer aided simulation of HEMT devices and circuits, if the HEMT is represented by an equivalent BC MOSFET as derived in this paper. The new representation can be useful for modeling of short-channel HEMT phenomena     

The gain and carrier density in semiconductor lasers understeady-state and transient conditions

The carrier distribution functions in a semiconductor crystal in the presence of a strong optical field are obtained. These are used to derive expressions for the gain dependence on the carrier density and on the optical intensity-the gain suppression effect. A general expression for high-order nonlinear gain coefficients is obtained. This formalism is used to describe the carrier and power dynamics in semiconductor lasers above and below threshold in the static and transient regimes     

Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs

We present an analytic, explicit and continuous charge model for a long-channel UTB (ultra-thin body) SOI (silicon-on-insulator) MOSFET, from which analytical expressions of the total capacitances are obtained. Our model is valid from below to well above threshold, without suffering from discontinuities between the regimes. It is based on a unified charge control model derived from Poisson’s equation. The drain-current, charge and capacitances expressions result in continuous explicit functions of the applied bias.The calculated capacitance characteristics are validated by 2D numerical simulations showing a very good agreement for different silicon film thicknesses.     

Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics.     

Grain boundary barrier height in base and space charge regions

The influence of grain boundary barrier height is of great importance for polycrystalline electronic devices and solar cells. The g.b. barrier height is computed in a forward biased one-sided step junction. Within the base, it is calculated by means of analytical expressions which depend on the interface state distribution. Within the space charge region, the population of the interface states is considerably changed on taking the band bending into account. In this region, the g.b. barrier height is obtained by means of a numerical solution of the two-dimensional Poisson's equation. The energy band diagram of the junction in the vicinity of the boundary is given. The variation of the g.b. barrier height as a function of the distance from the junction has been determined for monoenergetic and uniform interface state distributions and for different direct bias voltages.     

Interpretation of hall and resistivity measurements in polycrystalline silicon

Grain boundary barriers play a dominant role in the transport properties of polycrystalline silicon. As a result, resistivity and Hall measurements in polysilicon, when interpreted in the normal manner used for single crystals, do not represent in general the same physical entities as in single crystals. The bulk of the grain is more conducting and has a larger free carrier concentration than the barrier. However, the Hall voltage, from which the carrier concentration and mobility are computed, arises from both the bulk and the barrier region. For small grains (< 10μm) the contribution to the Hall voltage from the barrīer region is dominant, while for large grains (≥ 100μm) the bulk dominates. There is a transition region between the two. The magnitudes of the contributions depend on the relative size and resistivity of the grain and the boundary. Thus the interpretation of the data varies with grain size. Doping also affects the relative contribution of the bulk and barrier regions. It is not necessary to invoke carrier depletion within the grain to account for the observed mobility minimum.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.