Formation of thermal donors in SIMOX material

Thermal oxygen donor generation in SIMOX material formed in Czochralski (CZ) and oxygen free float zone (FZ) silicon was investigated by Hall and photoluminescence techniques. It was determined that residual interstitial oxygen was introduced to silicon by the SIMOX buried oxide formation process thus increasing the possibility of thermal donor creation. Significantly, thermal donor generation was identified and localized to the top silicon region in FZ material. The detected concentration of residual oxygen was on the order of 5 × 10¹³ cm^-3 and is negligible when compared to the intrinsic oxygen concentration of the starting CZ bulk material.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

应用于深亚微米DSOI器件的埋氧层的制备

利用低剂量、低能量的SIMOX（separation by implanted oxygen）图形化技术实现了深亚微米间隔埋氧层的制备．在二氧化硅掩膜尺寸为172nm的情况下，可以得到间隔为180nm的埋氧层．通过TEM（transmission electron microscope）观察发现埋层形貌完整、界面陡峭、无硅岛及其他缺陷．该结果为DSOI（dain/source on insulator）器件向更小尺寸发展奠定了工艺基础．     

SIMOX硅片埋氧层垂直方向热导率的测量

提出了一种简单、有效而且准确的测量SOI硅片埋氧层垂直方向热导率的方法,并采用这种方法测量了用SIMOX工艺制作的SOI硅片的埋氧层垂直方向的热导率.测量结果显示至少在5 5nm以上的尺度上对于SIMOX硅片的埋氧层垂直方向经典的热导率定义仍然成立,且为一明显小于普通二氧化硅的热导率(1 4W/mK)的常数1 0 6W/mK .测量中发现硅/二氧化硅边界存在边界热阻,并测量了该数值.结果表明,边界热阻在SOI器件尤其是薄二氧化硅背栅的双栅器件热阻的计算中不可忽略.     

SIMOX结构退化的卢瑟福背散射研究

在高温外延气氛下，ＳＩＭＯＸ结构会被损伤、退化。本文用卢瑟福背散射技术分析了这种退化，指出这种退化主要是高温下氢对表层硅的反应剥蚀及氢经表层硅中穿透性位错使埋层ＳｉＯ２分解。     

Electric-field-shielding layers formed by oxygen implantation into silicon

The electric-field-shielding effect was found in a layer consisting of a mixture of polycrystalline silicon and silicon oxide formed by oxygen ion implanatation. The layer was formed between the buried SiO2 and the upper Si layer, which improved characteristics for MOSFETs fabricated using SIMOX (separation by implanted oxygen) technology. By forming this layer, the threshold voltages for the MOSFETs were almost independent of substrate bias. Drain-to-source breakdown voltages for the p-MOSFETs and n-MOSFETs were raised to 250 V and 180 V, respectively.     

退火方式和气氛对SIMOX材料质量的影响

本文较为详细地研究了退火程序、退火气氛和注入方式对ＳＩＭＯＸ材料质量的影响，结果表明，采用二重或三重注入并在Ａｒ＋０．５％Ｏ２中退火，可以获得光滑平整的Ｓｉ／ＳｉＯ２界面和高质量的表面硅层。     

Analysis of persistent photoconductivity due to potential barriers

Persistent photoconductivity has been seen in thin silicon resistors fabricated with SIMOX material at temperatures between 60 and 220 K. This effect has been attributed to the depletion of carriers near the interface between the top silicon layer and the buried oxide, which is due to the large number of surface traps at this interface. The depletion of carriers is accompanied by a built-in field on the order of 10,000 V/cm, which causes a potential barrier that is nearly a quarter of the energy gap of silicon. The theory of the recombination kinetics of majority carriers with minority carriers trapped at the interface on the other side of a potential barrier is studied. Both the possibilities of tunneling and thermal activation have been considered. The results show that thermal activation dominates at the temperatures of our measurements in SIMOX material, while at lower temperatures tunneling would dominate.     

注氮工艺对SIMOX器件电特性的影响

研究了氮离子注入对SIMOX器件电特性的影响． 氮注入SIMOX的埋氧层并退火后，将减小前栅MOSFET/SIMOX的阈电压，提高其漏源击穿电压但对栅击穿电压影响较小.氮注入方式对SIMOX器件的I-V特性有重要影响．     

Temperature dependence of Hall mobility and electrical conductivity in SIMOX films

Transport data obtained on SIMOX films between 77 and 300 K are qualitatively different from those derived for bulk silicon. Results suggest a strong nonuniformity of carrier mobility: the uppermost part of the SIMOX layer is of comparable quality to bulk Si, but near the buried oxide there is a degradation, confirmed by prevailing coulombian scattering even at 300 K.     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。     

Practical reduction of dislocation density in SIMOX wafers

The dislocation density in the superficial silicon layers of SIMOX wafers formed under different oxygen implantation conditions has been investigated using a Secco etching technique. An extremely low dislocation density in the order of 10/sup 2/ cm/sup -2/ has been obtained for waters implanted at 180 keV with a dose of 0.4*10/sup 18/ and doses ranging from 0.9 to 1.2*10/sup 18/O/sup +//cm/sup 2/ at a wafer temperature of 550 degrees C followed by post-implant anneal at temperatures higher than 1300 degrees C. The buried oxide layers of the SIMOX wafers have breakdown voltages higher than 40 V.<>     

MESFETs in thin silicon on SIMOX

Si MESFETs have been built into a thin (100 nm) Si film on buried oxide implanted wafers. Aluminium has been used as gate material to obtain process compatibility with a high-performance CMOS process. With appropriate back bias the normally-on devices become enhancement-type. The high-quality SIMOX substrate provides excellent transconductance, while the thin film reduces two-dimensional effects.<>     

A macroscopic physical model and capacitive response of the buriedoxide having a transition layer in a SIMOX substrate

This paper proposes a macroscopic physical model for the buried oxide having a transition layer in a SIMOX substrate to estimate the parasitic capacitance. The Clausius-Mossotti relationship for two media is introduced into the model, employing an empirical factor to match with a high-frequency response. Peaks in the capacitance dependence on frequency appear only in devices with the buried oxide having a transition layer. This property can be explained by the proposed model. It is also shown that the transition layer adjacent to buried oxide should be eliminated to reduce parasitic capacitance     

Electron trapping in irradiated SIMOX buried oxides

Presented are new results of X-ray exposure of silicon-on-insulator devices fabricated on SIMOX (separation by implantation of oxygen) substrates. It is shown that the presence of numerous electron traps in the buried oxide may dominate the back-gate threshold voltage shift of strongly irradiated SIMOX transistors. A rebound effect occurs under a negative oxide field, due to the trapping of negative charges rather than to interface states generation. Irradiated transistors also show an increased sensitivity to hot-carrier effects     

CMOS／SIMOX和CMOS／BESOI的γ射线辐照特性比较

用薄膜ＳＩＭＯＸ（ＳｅｐａｒａｔｉｏｎｂｙＩＭｐｌａｎｔａｔｉｏｎｏｆＯＸｙｇｅｎ）、厚膜ＢＥＳＯＩ（ｆｆｅｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ）和体硅材料制备了ＣＭＯＳ倒相器电路，并用６０Ｃｏγ射线进行了总剂量辐照试验。在不同偏置条件下，经不同剂量辐照后，分别测量了ＰＭＯＳ、ＮＭＯＳ的亚阈特性曲线，分析了引起ＭＯＳＦＥＴ阈值电压漂移的两种因素（辐照诱生氧化层电荷和新生界面态电荷）。对ＮＭＯＳ／ＳＩＭＯＸ，由于寄生背沟ＭＯＳ结构的影响，经辐照后背沟漏电很快增大，经３００Ｇｙ（Ｓｉ）辐照后器件已失效。而厚膜ＢＥＳＯＩ器件由于顶层硅膜较厚，基本上没有背沟效应，其辐照特性优于体硅器件。最后讨论了提高薄膜ＳＩＭＯＸ器件抗辐照性能的几种措施。     

部分耗尽型注氟SIMOX器件的电离辐射效应

研究了采用向SIMOX圆片埋氧层中注入F离子的方法来改善SIMOX的抗总剂量辐射能力，通过比较未注F样品和注F样品的辐照前后SIMOX器件Ids-Vgs特性和阈值电压，发现F具有抑制辐射感生PMOSFET和NMOSFET阈值电压漂移的能力，并且可以减小NMOSFET中由辐照所产生的漏电流。说明在SOI材料中前后Si/Si02界面处的F可以减少空穴陷阱浓度，有助于提高SIMOX的抗总剂量辐射能力。     

β-SiC-on insulator waveguide structures for modulators and sensor systems

In this work waveguide structures using the cubic polytype of SiC are analyzed. The β-SiC-on-insulator wageguides were fabricated by two different methods. In the first case, a technological process similar to that used for SIMOX material was used, a buried SiO₂ layer being formed by high-energy (2 MeV) ion implantation of oxygen in SiC/Si wafers. For the second case, the heteroepitaxy of SiC on SOI (SIMOX) wafers was used. The losses of the waveguides have been measured at 0.633, 1.3 and 1.55 μm in both TE and TM polarization and a detailed analysis and interpretation of the different loss mechanisms is presented. Using these two types of waveguides we have designed waveguide modulators using the Pockels effect. A 2D semiconductor device simulator was used to determine the electric field configuration in a double-Schottky diode structure and the local modulation of the refractive index was used to determine the effective index modulation of the guided mode. Optical simulations were performed using the spectral index and the effective index methods. Different 2D geometries are analyzed and the material parameters needed for fabricating such a device are determined. Such devices have potential for high-speed Si-based photonic devices compatible with silicon technology.     

“Gated-diode” in SOI MOSFETs: a sensitive tool forcharacterizing the buried Si/SiO2 interface

A “gated diode” technique is described for the measurement of the interface state density of the silicon film/buried oxide interface of SOI MOSFETs. This approach becomes possible by taking advantage of the front gate, which is biased to inversion (NMOSFET) or accumulation (BC-PMOSFET) during the measurement, while scanning the back interface through depletion. Using this technique the estimated value of the buried interface state density of typical low dose SIMOX MOSFETs was slightly over 10¹¹/cm²