Design of tunneling injection quantum dot lasers

In recent years, semiconductor quantum dot (QD) lasers have attracted considerable attention due to their potentia applications[1]. Although QD laser has been predicted can have more excellent performance than conventional quan- tum well laser, so far tem…     

双量子环的隧穿电导和隧穿磁电阻

研究了双量子环的隧穿电导和隧穿磁电阻,研究结果表明:隧穿电导和隧穿磁电阻都随半导体环增大做周期性等幅振荡。δ势垒、Rashba自旋轨道耦合、AB磁通对隧穿电导或隧穿磁电阻的影响各不相同。隧穿磁电阻随AB磁通增强发生周期性等幅振荡,并随φ0角的减小而增大。两电极磁矩方向反平行时,隧穿磁电阻恒为零。     

Oxide roughness effect on tunneling current of MOS diodes

Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results.     

共振隧穿二极管(RTD)的物理模型——共振隧穿器件讲座(3)

介绍了共振隧穿二极管物理模型的量子力学基础,重点讲解共振隧穿两种物理模型,从不同维度隧穿的特点分析共振隧穿和非共振隧穿的区别,为以后讨论分析共振隧穿器件的特性奠定基础。     

Effects of neglecting carrier tunneling on electrostatic potentialin calculating direct tunneling gate current in deep submicron MOSFETs

We investigate the validity of the assumption of neglecting carrier tunneling effects on the self-consistent electrostatic potential in calculating the direct tunneling gate current in deep submicron MOSFETs. A comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high-K gate dielectrics     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

基于阳极键合干法刻蚀技术的MEMS隧道加速度计的加工及测试

提出了一种基于北京大学硅玻璃键合深刻蚀释放工艺的扩展工艺,用来加工微型隧道加速度计.采用HP4145B半导体分析仪在大气环境下对所加工的器件进行了开环测试,验证了隧道电流的存在以及隧道间隙与隧道电流之间的指数关系.实验结果外推出的隧道势垒的范围为1.182～2.177eV.大部分器件的开启电压在14～16V之间.在-1,0和+1g三种状态下对开启电压分别进行了测试,得到加速度计的灵敏度约为87mV/g.     

谐振式隧穿磁强计的理论研究

分析了隧道扫描显微镜和隧穿磁强计的区别 ,认为隧穿磁强计的隧尖不需要也不应该过尖。研究了隧道间隙和隧道电流的关系。研究表明 ,虽然按照隧道效应理论 ,隧道间隙和隧道电流应该成指数关系 ,但对隧穿磁强计而言 ,其隧道电流和隧道间隙的关系可以近似看作线性关系。推导了谐振式隧穿磁强计的灵敏度计算公式     

微机械电子隧道传感器研究进展

说明了微机械电子隧道传感器的工作原理，分析了电子隧道传感器的优点。较系统地介绍了几种典型的微机械电子隧道传感器包括微机械电子隧道加速度计、红外探测器和磁强计等，并简要介绍了国际上在这个领域的研究机构     

一维单势垒光量子阱中多通道特性分析

用传输矩阵法研究了形式为(AB)m(CD)n(BA)m的一维单势垒光量子阱结构的隧穿通道特性。研究结果表明,阱层周期数决定了光量子阱中隧穿通道个数。垒层周期数对通道位置、个数、间距无调控作用。晶格常数变大,能明显调节隧穿通道的位置及间距,且晶格常数越小,通道越精细。入射角变化可对通道的位置、间距进行微调,且角度越大,通道越精细。该特性可为设计可调多通道光学滤波器等量子光学器件提供指导。     

新型电子器件和光学器件的共振隧穿结构

描述了一种新型共振隧穿结构器件，这种器件包含了通过可变间隙超晶格能量滤波器（ＶＳＳＥＦ）中的耦合量子附态的隧穿过程．论证了通过ＡｌＡｓ／ＧａＡｓＶＳＳＥＦ器件高能态和ＡｌＧａＡｓ／ＧａＡｓ超晶格受激态的共振隧穿，描述了这种器件作为较高功率微波源和共振隧穿晶体管的应用，并讨论了共振隧穿结构作为雪崩探测器和红外发射器等光学器件的潜在应用．     

First-principles study of the effects of oxygen vacancy on hole tunneling current

The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field.     

The scanning tunneling microscopy and scanning tunneling spectroscopy of amorphous carbon

The most important methods for studying the surface of amorphous diamond-like carbon are scanning tunneling microscopy and scanning tunneling spectroscopy. In this review, publications concerned with studying the topography and electronic properties of the surface of amorphous diamond-like carbon films using a tunneling microscope are considered; related publications devoted to the microprobe study of field emission from amorphous carbon and to the tunneling microscopy of metal-carbon nanocomposites are also reviewed.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Superconductive tunneling

This paper reviews briefly the tunneling mechanisms through a thin insulating barrier between two metals and mentions some device applications based on these mechanisms. Three different cases are described: tunneling between metals both in the normal (nonsuperconductive) state, tunneling between them when one or both are superconductive, and Josephson tunneling through a very thin barrier between superconductors.     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

Tunneling time asymmetry in semiconductor heterostructures

Analytical expressions are given for the difference between left-to-right and right-to-left tunneling times in asymmetric single- and multiple-barrier heterostructures. This tunneling time asymmetry is related to the phase difference of the reflection coefficients of the electron wavefunction for the two tunneling directions. Examples for single- and double-barrier heterostructures are given. The treatment in this paper can be used for designing devices with asymmetric frequency characteristics with respect to the electron tunneling direction     

A new I-V model for stress-induced leakage current includinginelastic tunneling

A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant