一种单片集成的CMOS数/模接口电路的设计

介绍了一种单片集成的数模接口电路。它主要由两个8位D/A转换器、8个比较器通道和片上带隙基准源组成。设计中,采用了一种规则的全NMOS管构成的M-2M梯形电路,以及本文提出的电流-电压转换电路。电路采用1.2μm双层多晶双层金属N阱CMOS工艺实现,芯片面积3.5mm×2.7mm。系统采用5V双电源,正常工作时功耗约为500mW。D/A转换器的有效工作位为7位,实现了确定的-3V到+3.5V的输出幅度,满摆幅输出建立时间小于1μs。比较器通道的传输延迟小于10ns。     

高速SOIMOS器件及环振电路的研制

设计了一种 1 0位 50 MS/s双模式 CMOS数模转换器 .为了降低功耗 ,提出了一种修正的超前恢复电路 ,在数字图象信号输出中 ,使电路功耗降低约 30 % .电路用 1μm工艺技术实现 ,其积分线性误差为 0 .46LSB,差分线性误差为 0 .0 3LSB.到± 0 .1 %的建立时间少于 2 0 ns.该数模转换器使用 5V单电源 .在 50 MS/s时全一输入时功耗为 2 50 m W,全零输入时功耗为 2 0 m W,电路芯片面积为 1 .8mm× 2 .4mm.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种10bit 200MS/s电流型DAC设计

基于SMIC 0.18μm CMOS工艺,采用了具有电荷抽放技术的电流源结构,以及新型锁存电路产生同步控制信号.设计了一个10位精度的数模转换器(DAC),电源电压为1.8 V,在50负载条件下,DAC满量程输出电流为4mA.当采样频率为200 MHz,输入频率为5 MHz的情况下.满量程功耗为15 mw.微分非线性误差(DNL)为0.25 LSB,积分非线性误差(INL)为0.15 LSB,无杂散动态范围达到79.7 dB.     

一种高速电流型CMOS数模转换器设计

设计了一种10位50MS/s双模式CMOS数模转换器.为了降低功耗,提出了一种修正的超前恢复电路,在数字图象信号输出中,使电路功耗降低约30%.电路用1μm工艺技术实现,其积分线性误差为0.46LSB,差分线性误差为0.03LSB.到±0.1%的建立时间少于20ns.该数模转换器使用5V单电源.在50MS/s时全一输入时功耗为250mW,全零输入时功耗为20mW,电路芯片面积为1.8mm×2.4mm.     

AD9708及其在数据采集系统中的应用

概述AD9708是ANALOG公司生产的TxDAC系列数模转换器。它是采用单电源供电的低功耗电流输出型14位并行高速数模转换器。AD9708采用 3V或 5V单电源供电,两路电流输出,转换速率高达125MHz,建立时间不大于35ns,转换精度为1/4 LSB。在 5V电源供电的情况下,其功耗为175mW;在 3V电源供     

一种低功耗嵌入式14位400MHz数模转换器

设计了一个14位刷新频率达400MHz,用于高速频率合成器的低功耗嵌入式数模转换器。该数模转换器采用5+4+5分段式编码结构,其电流源控制开关输出驱动级采用归零编码以提高DAC动态特性。该数模转换器核采用0.18μm1P6M混合信号CMOS工艺实现,整个模块面积仅为1.1mm×0.87mm。测试结果表明,该DAC模块的微分非线性误差是-0.9～+0.5LSB,积分非线性误差是-1.4～+1.3LSB,在400MHz工作频率下,输出信号频率为80MHz时的无杂散动态范围为76.47dB,并且功耗仅为107.2mW。     

0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

12位80MHz采样率具有梯度误差补偿的CMOS电流舵D/A转换器实现

提出了一种12位80MHz采样率具有梯度误差补偿的电流舵D/A转换器实现电路.12位DAC采用分段式结构,其中高8位采用单位电流源温度计码DAC结构,低4位采用二进制加权电流源DAC结构,该电路中所给出的层次式对称开关序列可以较好地补偿梯度误差.该D/A转换器采用台湾UMC 2层多晶硅、2层金属(2P2M)5V电源电压、0.5μm CMOS工艺生产制造,其积分非线性误差小于±0.9LSB,微分非线性误差小于±0.6LSB,芯片面积为1.27mm×0.96mm,当采样率为50MHz时,功耗为91.6mW.     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB Dynamic Range

A 1.5 V, 12-bit, 16 MSPS analog-to-digital converter was implemented in 0.25 μm 1P5 M standard CMOS process with MIM capacitors. The converter achieves a peak SNDR of 66.5 dB with 5.12 MSPS and that of 63.0 dB with 16.384 MSPS. The dynamic range is 68 dB under both sampling rates. The maximum INL of ±0.8 LSB and DNL of ±0.5 LSB were measured under 5.12 MSPS, while those of 16.384 MSPS decreased to ±3.1 and ±1.0 LSB, respectively. An embedded bandgap reference circuit that provides the conversion voltage range is also presented with 1.5 V supply voltage. The total power consumption of this converter was 138 mW under 16.384 MSPS or 97 mW under 5.12 MSPS. The total area of this chip is 2.8 × 2.5 mm. This chip was implemented without calibration or trimming approaches.     

一种1.5 V 8位100 MS/s电流舵D/A转换器

基于新型的低压与温度成正比(PTAT)基准源和PMOS衬底驱动低压运算放大器技术,采用分段温度计译码结构设计了一种1.5V8位100MS/s电流舵D/A转换器,工艺为TSMC0.25μm2P5MCMOS。当采样频率为100MHz,输出频率为20MHz时,SFDR为69.5dB,D/A转换器的微分非线性误差(DNL)和积分非线性误差(INL)的典型值分别为0.32LSB和0.52LSB。整个D/A转换器的版图面积为0.75mm×0.85mm,非常适合SOC的嵌入式应用。     

10比特200Msps电流舵DAC的设计

实现了一款10比特200Msps采样速度的数模转换器。该数模转换器采用了8+2的分段结构,高8位比特使用温度码设计。文中详细分析了CMOS工艺下匹配问题,采取一定措施提高匹配性。该数模转换器采用3.3V供电电压,摆幅为2Vpp,提高了系统的抗干扰能力。在200Msps采样率下,后仿真结果可达到INL小于0.34LSB,DNL小于0.05LSB,有效比特数为9.9,SNDR达到61.7dB,SFDR为75.3dB。该DAC采用SMIC180nm CMOS工艺设计,整体面积为800*800μm2。     

A cyclic A/D converter that does not require ratio-matchedcomponents

The circuit configuration of a cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is described. The analog portion of the circuit consists of two operational amplifiers, four capacitors, and ten switches regardless of the number of bits per sample converted, and completes an n-bit conversion in 3n clock cycles. The conversion characteristics are inherently insensitive both to capacitor ratio and to amplifier offset voltage. The circuit, therefore, can be realized in a small die area. The effects of finite amplifier gain and switch charge injection on the conversion accuracy are discussed. A prototype chip has been fabricated in a 2-μm CMOS technology operating on a single 5-V supply. When it is operated as an 8-bit converter at a sampling rate of 8 kHz, the maximum conversion error is 0.2 LSB (least-significant bit) for differential nonlinearity and 0.5 LSB for integral nonlinearity. The die area measures 0.79 mm²     

一种用于半并行A/D转换器的比较器设计

简要介绍了半并行结构的A/D转换器原理。针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器。解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题。给出了应用该比较器的0.6μm CMOS半并行A/D转换器的性能。结果表明,设计的比较器能使丰并行ADC的DNL和INL小于±0.5 LSB,SNR大于48dB。     

一种基于0.13m CMOS工艺的10位SAR A/D转换器

基于SMIC0.13μm CMOS1P6M Logic工艺,采用一种新型R-C组合式D/A转换结构、伪差分比较结构以及低功耗电平转换结构设计了一种用于多电源SoC的10位8通道逐次逼近型A/D转换器。在3.3V模拟电源电压和1.2V数字电源电压下,测得DNL和INL分别为0.31LSB和0.63LSB。当采样频率为1MS/s,输入信号频率为490kHz时,测得的SFDR为67.33dB,ENOB为9.48bits,功耗为3.25mW。该A/D转换器版图面积为318μm×270μm,能直接应用于嵌入式多电源SoC。     

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs(most-significant-bits)-plus-5 LSBs(least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach,with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method,an 8-channel 10-bit 200-kS/s SAR ADC(successive-approximation -register analog-to-digital converter) IP core for a touch screen SoC(system-on-chip) is implemented in a 0.18μm 1P5M CMOS logic process.Design considerations for the touch sc...     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than ±0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8-μm CMOS technology and occupies an area of 2.6×2.5 mm²